Physical Design Contractor

Overview

Hybrid
$80 - $100
Contract - W2
Contract - Independent
Contract - 12 Month(s)

Skills

STA

Job Details

Your primary responsibilities will include:

  • End-to-End Physical Design Execution: Own and execute the digital physical design flow from RTL to GDSII using the Cadence tool suite, including Genus (synthesis), Innovus (place and route), and Tempus (timing analysis and closure).
  • Design Integration: Integrate and manage complex digital blocks and subsystems, ensuring seamless interaction with analog and quantum components.
  • Physical Verification and Signoff: Guide designs through physical checking and verification processes, including DRC, LVS, and other signoff criteria, to ensure manufacturability and compliance with foundry requirements.
  • Tapeout Delivery: Drive designs to successful RIT (Release to Tapeout), ensuring all physical and timing signoff requirements are met.
  • Collaboration and Communication: Work closely with circuit designers, researchers, and tool developers to resolve design challenges, optimize flows, and ensure alignment across disciplines.
  • Problem Solving and Debug: Apply strong analytical and debugging skills to identify and resolve design and flow issues, with a focus on quality and efficiency.
  • Continuous Improvement: Contribute to the development and refinement of physical design methodologies, leveraging scripting and automation to enhance productivity and design quality.
  • Innovation Support: Engage with emerging technologies and methodologies, including those relevant to quantum computing, to help shape the future of chip design.

This role requires a proactive, detail-oriented engineer with a passion for innovation and a strong foundation in digital physical design. You will be part of a dynamic team pushing the boundaries of what s possible in quantum hardware.

About the Team
The Quantum team is highly technical with a strong record for excellence in delivery and innovation. In addition to local collaboration, these teams interact closely with multi-site Microprocessor/ASICs and System teams as well as The Research Group to enable Microprocessor/System, Quantum, Storage, and AI roadmaps.

Required Professional and Technical Expertise

  • BS Computer/Electrical Engineering or related
  • 5+ years of experience with industry-standard Physical Design tools such as the Cadence tool suite, including Genus, Innovus, & Tempus (e.g. timing closure)
  • Knowledge of physical checking and verification (e.g. DRC/LVS)
  • Excellent problem-solving skills
  • Demonstrated ability to contribute and collaborate effectively within diverse teams
  • Strong verbal and written communication skills
  • Demonstrated ability to embrace and overcome challenges
  • Demonstrated ability to remain adaptable in a dynamic environment
  • Demonstrated ability to deliver high-quality deliverables with a strong attention to detail

Preferred Professional and Technical Expertise

  • Proficiency in scripting languages (e.g. Python, Tcl, SKILL)
  • Ability to develop and deepen skills through continuous learning and a growth mindset
  • Demonstrated ability to drive innovation and adopt emerging tools and methodologies
  • Transistor-level layout knowledge using tools such as Cadence Virtuoso, and design languages like SKILL
  • Bonus: Knowledge of quantum computing

Required Education

Bachelor's Degree

Preferred Education

Master's Degree

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