Overview
Skills
Job Details
Job Title: Circuit Design Engineer (Active Secret Clearance required)
Duration: 12 Months Contract
Location: Lexington, MA 02421, United States (Part Time Remote Role)
Job Overview:
Work from Home: This position is REMOTE. The candidate is able to work remotely from any location. They may be asked to take up to 3+ trips per calendar year to Lexington if the program/project requires it.
Hours: This position is a part time role with up to 24hrs a week.
Job Description:
Designs and develops circuits used in electronic devices. Responsible for layout and mask design, device evaluation and characterization, test box design, prototype construction and checkout, and determination of wafer fabrication processes. Prepares test methods and specifications; analyzes equipment to establish operating data and conducts experimental tests; provides finished device approval; and prepares customer application information.
Background/Need:
Group 87 develops custom digital & mixed-signal Readout Integrated Circuits (ROICs) for advanced imager applications. An analog/mixed-signal layout design engineer is needed for implementation of imager circuit building blocks.
Responsibilities include but are not limited to:
Physical layout and verification of integrated circuit building blocks
Full-chip assembly and top-level verification.
Use best-practices for managing local process variation through layout techniques as well as high-speed digital and RF layout techniques to minimize unwanted parasitic interactions.
Must Have:
Experience in deep-submicron CMOS layout across technologies including 12-65 nm design nodes in multiple foundries such as Global Foundries, onsemi and Tower Jazz
Cadence integrated circuit design flow including layout, DRC, LVS and parasitic extraction through the use of Calibre and Assura.
Proven track record of multiple design tape outs
Extensive experience in top level floor planning as well as block level design
Strong interpersonal and organizational skills along with strong written/verbal skills are required to support a multi-person design team in an effective way.
Other:
- Clearance: An ACTIVE clearance is required for this role.
- Interview Process: 1st round will be a Zoom with the hiring manager. 2nd round will be a Zoom with additional team members as needed.
Qualification Table | ||
Design | Must Have | Total Experience |
Cadence IC design flow with layout, DRC, LVS, and parasitic extraction using Calibre and Assura | 10 years |
|
Experience in top level floor planning as well as block level design | 10 years |
|
Experience | Must Have | Total Experience |
Currently holds a Secret Clearance (OR a higher clearance) | Yes |
|
Deep-submicron CMOS Layout (12nm - 22nm, Global Foundries) | 10 years |
|
Soft Skills | Must Have | Total Experience |
Strong team communication | Yes |
|
Strong Verbal and Written Communication | Yes |
|