Overview
On Site
Depends on Experience
Contract - W2
Contract - 6 Month(s)
Skills
ICC
Integrated Circuit
Mixed-signal Integrated Circuit
Physical Data Model
Static Timing Analysis
Synopsys
Timing Closure
Writing
Job Details
Physical Design Engineer
Contract
First preference : CA
Second preference: Anywhere in the US
Expected Start Date: 1st week of June
Client: TESSOLVE
Mandatory Skills/Experience
Experience in leading and executing Full-chip Hierarchical Physical Design of Mixed-signal chips.
Experience in understanding and writing synthesis design constraints for hierarchical physical partitions
Experience in STA and Timing closure for very high-speed designs >1 GHz
Experience with TSMC 12FFC node and other FINFET nodes (desirable)
Experience with Synopsys ICC2 based P&R flow
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