Senior ASIC Engineer

Position: Senior ASIC Engineer Location: San Diego, CA (Candidate needs to work Day 1 onsite)
Work Arrangement Fully On-Site
Duration: 12 Months Experience level: 8- 15 Years
This role has strong experience in System Verilog, UVM, DDR PHY / LPDDR protocol, Power-aware simulations.

What You'll Be Doing:
Work involves executing complete verification project in the role of Senior engineer with hands on experience, mentoring, client communication / interactions, in-depth technical reviews and close tracking of technical as well as management aspects.
Very much adaptive to demanding situation and fast decision maker.
What We Are Looking For: Technical:
At-least 5+ years of experience in System Verilog HVL.
At-least 5+ year of experience in UVM.
Experience with VIP development primarily experienced in DDR PHY / LPDDR protocol
Experience in complete verification cycle which includes development of test plan, BFM/Driver/Monitor/Scoreboard component development and integration in test bench, stress/corner testing, failure debug, gate level simulations, assertions and coverage closure.
Proficient in SVTB/UVM
Analog+Digital co-verification experience
Proficient in debug and assertions coding
Gate level simulation experience
Expert in Power aware simulations
Make/Perl/Python
Ensure customer satisfaction.
Reporting to customer on daily or weekly progress effectively