Overview
On Site
USD 150,000.00 - 250,000.00 per year
Full Time
Skills
Telecommunications
Science
Electrical Engineering
Computer Science
Digital Signal Processing
Verilog
SystemVerilog
RTL
Timing Closure
FPGA
Xilinx
IDE
Military
SAP BASIS
Authorization
Law
LOS
Recruiting
Legal
Artificial Intelligence
Privacy
Job Details
Principal RTL Design Engineer / Senior FPGA Design Engineer Needed for Leading Telecom Company!
This Jobot Job is hosted by: Reed Kellick
Are you a fit? Easy Apply now by clicking the "Apply Now" button and sending us your resume.
Salary: $150,000 - $250,000 per year
A bit about us:
Based in Irvine, are a growing division of a leading telecom company that is on the lookout for a talented Staff RTL Design Engineer / Principal FPGA Design Engineer!
Why join us?
As a Lead RTL Design Engineer / Staff FPGA Design Engineer in our company, we are able to offer:
Job Details
As a Senior RTL Engineer / Lead FPGA Design Engineer on our team, we are looking for:
Interested in hearing more? Easy Apply now by clicking the "Apply Now" button.
Jobot is an Equal Opportunity Employer. We provide an inclusive work environment that celebrates diversity and all qualified candidates receive consideration for employment without regard to race, color, sex, sexual orientation, gender identity, religion, national origin, age (40 and over), disability, military status, genetic information or any other basis protected by applicable federal, state, or local laws. Jobot also prohibits harassment of applicants or employees based on any of these protected categories. It is Jobot's policy to comply with all applicable federal, state and local laws respecting consideration of unemployment status in making hiring decisions.
Sometimes Jobot is required to perform background checks with your authorization. Jobot will consider qualified candidates with criminal histories in a manner consistent with any applicable federal, state, or local law regarding criminal backgrounds, including but not limited to the Los Angeles Fair Chance Initiative for Hiring and the San Francisco Fair Chance Ordinance.
Information collected and processed as part of your Jobot candidate profile, and any job applications, resumes, or other information you choose to submit is subject to Jobot's Privacy Policy, as well as the Jobot California Worker Privacy Notice and Jobot Notice Regarding Automated Employment Decision Tools which are available at jobot.com/legal.
By applying for this job, you agree to receive calls, AI-generated calls, text messages, or emails from Jobot, and/or its agents and contracted partners. Frequency varies for text messages. Message and data rates may apply. Carriers are not liable for delayed or undelivered messages. You can reply STOP to cancel and HELP for help. You can access our privacy policy here: jobot.com/privacy-policy
This Jobot Job is hosted by: Reed Kellick
Are you a fit? Easy Apply now by clicking the "Apply Now" button and sending us your resume.
Salary: $150,000 - $250,000 per year
A bit about us:
Based in Irvine, are a growing division of a leading telecom company that is on the lookout for a talented Staff RTL Design Engineer / Principal FPGA Design Engineer!
Why join us?
As a Lead RTL Design Engineer / Staff FPGA Design Engineer in our company, we are able to offer:
- A competitive base salary between $150k and $250k!
- 401k!
- Medical, dental and vision coverage!
- PTO/vacation!
- Work from home / work remote on Tuesdays and Fridays!
Job Details
As a Senior RTL Engineer / Lead FPGA Design Engineer on our team, we are looking for:
- Bachelor of Science degree in Electrical Engineering, Computer Science, or relevant fields.
- Minimum 3 years of demonstrated experience in RTL design and FPGA implementation; Proven experience in RTL design and FPGA implementation with an advanced degree (MS or PhD) in Electrical Engineering, Computer Science, or relevant fields.
- Demonstrated experience with fixed point binary arithmetic and digital signal processing designs.
- Deep knowledge of RTL design fundamentals using Verilog and System-Verilog.
- Proven expertise working with front-end RTL design tools, FPGA synthesis, timing closure, multiple clock-domain and/or high-utilization FPGA designs.
- Experience with Xilinx FPGAs, SoCs, and the Vivado IDE.
Interested in hearing more? Easy Apply now by clicking the "Apply Now" button.
Jobot is an Equal Opportunity Employer. We provide an inclusive work environment that celebrates diversity and all qualified candidates receive consideration for employment without regard to race, color, sex, sexual orientation, gender identity, religion, national origin, age (40 and over), disability, military status, genetic information or any other basis protected by applicable federal, state, or local laws. Jobot also prohibits harassment of applicants or employees based on any of these protected categories. It is Jobot's policy to comply with all applicable federal, state and local laws respecting consideration of unemployment status in making hiring decisions.
Sometimes Jobot is required to perform background checks with your authorization. Jobot will consider qualified candidates with criminal histories in a manner consistent with any applicable federal, state, or local law regarding criminal backgrounds, including but not limited to the Los Angeles Fair Chance Initiative for Hiring and the San Francisco Fair Chance Ordinance.
Information collected and processed as part of your Jobot candidate profile, and any job applications, resumes, or other information you choose to submit is subject to Jobot's Privacy Policy, as well as the Jobot California Worker Privacy Notice and Jobot Notice Regarding Automated Employment Decision Tools which are available at jobot.com/legal.
By applying for this job, you agree to receive calls, AI-generated calls, text messages, or emails from Jobot, and/or its agents and contracted partners. Frequency varies for text messages. Message and data rates may apply. Carriers are not liable for delayed or undelivered messages. You can reply STOP to cancel and HELP for help. You can access our privacy policy here: jobot.com/privacy-policy
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.