Emulation Engineer (HAPS)

Job Description:

We are seeking a highly experienced FPGA Emulation & HAPS Specialist to join our engineering team. The ideal candidate will be proficient in HAPS system setup, FPGA prototyping, and emulation design, with a solid background in ASIC design and functional verification. You will work on advanced projects involving Cadence Palladium (Z2) and Synopsys HAPS-100 systems, contributing to the full verification and emulation cycle.

Key Responsibilities:

• Set up and manage HAPS systems, including bring-up, debugging, and issue triaging
• Build and execute the complete HAPS flow, not just image building
• Collaborate with software and hardware validation teams
• Understand and support testbench architecture in emulation environments
• Perform system-level emulation and validation using Cadence Palladium and Synopsys HAPS
• Conduct gate-level simulations, stress testing, failure debug, and coverage closure
• Contribute to testbench and UVM component development, including BFM, drivers, monitors, and scoreboards

Required Skills & Experience:

• 10+ years of experience in ASIC or related fields with a Bachelor s degree, or 8+ years with a Master s degree
• 2+ years of hands-on experience in emulation (Cadence Palladium and/or Synopsys HAPS)
• Strong background in SystemVerilog/UVM (SV/UVM)
• Expertise in FPGA design, including partitioning multi-million gate designs across multiple FPGAs
• Proficient in C++ testbench, SVTB/UVM development, and verification methodologies
• Understanding of software-hardware co-validation environments

Must-Have Skills:

• HAPS system setup and debug
• FPGA Prototyping
• Emulation Design

Preferred Qualifications:

• Experience with test plan creation, assertions, and coverage analysis
• Familiarity with gate-level simulation and performance debugging

Education: Bachelor s or Master s in Electrical or Computer Engineering