Overview
On Site
$75 - $85
Contract - W2
Contract - 6 Month(s)
No Travel Required
Skills
Apache Subversion
Artificial Intelligence
Build Tools
C
C++
Computer Engineering
Computer Networking
Data Analysis
EDA
Electrical Engineering
Emulation
Version Control
Verilog
Shell
Open Verification Methodology
Git
IP
Intellectual Property
Machine Learning (ML)
Mercurial
Perl
Python
ROOT
Scripting
System On A Chip
SystemVerilog
Test Plans
UVM
Video
Job Details
Mandatory Experience:
- 7 + years experience in architecting and implementing Design Verification infrastructure and executing the complete verification cycle
- Experience in the development of UVM based verification environments from scratch
- Experience with Design verification of Data-center applications like Video, AI/ML, and Networking designs
Minimum Qualifications
- B.S or M.S degree in Electrical Engineering, Computer Engineering or Computer Science
- Hands-on experience in Verilog, System Verilog, C/C++ based verification, and UVM methodology
- Experience in IP/sub-system and/or SoC level verification based on System Verilog UVM/OVM based methodologies
- Experience in EDA tools and scripting (Python, Perl, Shell) used to build tools and flows for verification environments.
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