Senior FPGA Verification Engineer

We are looking for an experienced FPGA Verification Engineer to verify complex FPGA designs. You will develop and execute verification plans, debug issues, and ensure high-quality, reliable products.

Responsibilities:

• Develop and maintain test benches using UVM/SystemVerilog.
• Write and debug test cases for functional and performance validation.
• Identify and resolve design issues in collaboration with engineering teams.
• Participate in design reviews and contribute to verification strategy.
• Stay current with the latest verification tools and methodologies.
• Strong knowledge of FPGA, ASIC, and RTL design.
• Hands-on experience with SystemVerilog, UVM, and tools like QuestaSim, VCS, or Haps.
• Familiar with Linux and scripting (Python/Perl preferred).
• Experience with high-speed I/O and protocols (PCIe, I2C, SPI).
• Proficiency with lab tools (logic analyzer, oscilloscope, JTAG).
• Strong debugging and communication skills.
• Strong knowledge of FPGA, ASIC, and RTL design.
• Hands-on experience with SystemVerilog, UVM, and tools like QuestaSim, VCS, or Haps.
• Familiar with Linux and scripting (Python/Perl preferred).
• Experience with high-speed I/O and protocols (PCIe, I2C, SPI).
• Proficiency with lab tools (logic analyzer, oscilloscope, JTAG).
• Strong debugging and communication skills.
• Experience in hardware validation or test automation.
• Exposure to VHDL or Verilog.