Overview
Remote
On Site
USD50 - USD80 per hour, Benefits: $50-80
Full Time
Skills
Engineer
Engineering
Job Details
Sr SoC Gate-Level Simulation (GLS) Engineer
In need of a solid Gate-Level Simulation Engineer to support complex System-on-Chip (SoC) development. In this contract role, you ll be responsible for verifying gate-level functionality, timing, and power across SoC subsystems. You'll work closely with RTL, physical design, and verification teams to ensure accurate coverage and system-level stability.
Scope:
Develop and apply GLS methodologies for high-performance SoC projects
Run gate-level simulations to validate functionality, timing closure, and power integrity
Build and execute test plans at both IP and full-chip levels
Work with RTL, verification, and implementation teams to resolve simulation failures and timing issues
Analyze waveforms and logs, debug issues down to netlist or RTL root causes
Validate timing-critical paths, async crossings, and power-down flows
Automate simulation workflows to boost coverage and repeatability
Maintain and improve SoC-level simulation tools and infrastructure
Document simulation strategies, workflows, and technical best practices
Required:
Bachelor s or Master s in Electrical or Computer Engineering (or related field)
Hands-on experience with GLS for SoCs or large IP blocks
Solid knowledge of ASIC flows, including Liberty/SDF and physical design concepts
Expertise in Verilog/VHDL, simulation tools (e.g., VCS, Xcelium, Questa)
Proficiency in Python, Perl, or TCL scripting
Familiarity with UPF/CPF and low-power simulation strategies
Strong skills in debugging timing mismatches and convergence issues
Pluses:
Experience correlating GLS behavior with post-silicon validation
Knowledge of power gating, clock gating, and their effects on simulation
Familiarity with STA, IR drop, and power simulation techniques
Exposure to SoC domains such as AI/ML accelerators, video, or networking
Understanding of standard protocols: PCIe, DDR, USB, AXI, NoC
Estimated Min Rate: $50.00
Estimated Max Rate: $80.00
What s In It for You?
We welcome you to be a part of the largest and legendary global staffing companies to meet your career aspirations. Yoh s network of client companies has been employing professionals like you for over 65 years in the U.S., UK and Canada. Join Yoh s extensive talent community that will provide you with access to Yoh s vast network of opportunities and gain access to this exclusive opportunity available to you. Benefit eligibility is in accordance with applicable laws and client requirements. Benefits include:
Note: Any pay ranges displayed are estimations. Actual pay is determined by an applicant's experience, technical expertise, and other qualifications as listed in the job description. All qualified applicants are welcome to apply.
Yoh, a Day & Zimmermann company, is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.
Visit https://www.yoh.com/applicants-with-disabilities to contact us if you are an individual with a disability and require accommodation in the application process.
For California applicants, qualified applicants with arrest or conviction records will be considered for employment in accordance with the Los Angeles County Fair Chance Ordinance for Employers and the California Fair Chance Act. All of the material job duties described in this posting are job duties for which a criminal history may have a direct, adverse, and negative relationship potentially resulting in the withdrawal of a conditional offer of employment.
In need of a solid Gate-Level Simulation Engineer to support complex System-on-Chip (SoC) development. In this contract role, you ll be responsible for verifying gate-level functionality, timing, and power across SoC subsystems. You'll work closely with RTL, physical design, and verification teams to ensure accurate coverage and system-level stability.
Scope:
Develop and apply GLS methodologies for high-performance SoC projects
Run gate-level simulations to validate functionality, timing closure, and power integrity
Build and execute test plans at both IP and full-chip levels
Work with RTL, verification, and implementation teams to resolve simulation failures and timing issues
Analyze waveforms and logs, debug issues down to netlist or RTL root causes
Validate timing-critical paths, async crossings, and power-down flows
Automate simulation workflows to boost coverage and repeatability
Maintain and improve SoC-level simulation tools and infrastructure
Document simulation strategies, workflows, and technical best practices
Required:
Bachelor s or Master s in Electrical or Computer Engineering (or related field)
Hands-on experience with GLS for SoCs or large IP blocks
Solid knowledge of ASIC flows, including Liberty/SDF and physical design concepts
Expertise in Verilog/VHDL, simulation tools (e.g., VCS, Xcelium, Questa)
Proficiency in Python, Perl, or TCL scripting
Familiarity with UPF/CPF and low-power simulation strategies
Strong skills in debugging timing mismatches and convergence issues
Pluses:
Experience correlating GLS behavior with post-silicon validation
Knowledge of power gating, clock gating, and their effects on simulation
Familiarity with STA, IR drop, and power simulation techniques
Exposure to SoC domains such as AI/ML accelerators, video, or networking
Understanding of standard protocols: PCIe, DDR, USB, AXI, NoC
Estimated Min Rate: $50.00
Estimated Max Rate: $80.00
What s In It for You?
We welcome you to be a part of the largest and legendary global staffing companies to meet your career aspirations. Yoh s network of client companies has been employing professionals like you for over 65 years in the U.S., UK and Canada. Join Yoh s extensive talent community that will provide you with access to Yoh s vast network of opportunities and gain access to this exclusive opportunity available to you. Benefit eligibility is in accordance with applicable laws and client requirements. Benefits include:
- Medical, Prescription, Dental & Vision Benefits (for employees working 20+ hours per week)
- Health Savings Account (HSA) (for employees working 20+ hours per week)
- Life & Disability Insurance (for employees working 20+ hours per week)
- MetLife Voluntary Benefits
- Employee Assistance Program (EAP)
- 401K Retirement Savings Plan
- Direct Deposit & weekly epayroll
- Referral Bonus Programs
- Certification and training opportunities
Note: Any pay ranges displayed are estimations. Actual pay is determined by an applicant's experience, technical expertise, and other qualifications as listed in the job description. All qualified applicants are welcome to apply.
Yoh, a Day & Zimmermann company, is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.
Visit https://www.yoh.com/applicants-with-disabilities to contact us if you are an individual with a disability and require accommodation in the application process.
For California applicants, qualified applicants with arrest or conviction records will be considered for employment in accordance with the Los Angeles County Fair Chance Ordinance for Employers and the California Fair Chance Act. All of the material job duties described in this posting are job duties for which a criminal history may have a direct, adverse, and negative relationship potentially resulting in the withdrawal of a conditional offer of employment.
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.