Analog Layout Engineer x3

Position: Analog Layout Design Engineer Location: Santa Clara, CA
Contract Type: 3-Month Contract-to-Hire

Responsibilities:

• Perform layout of cutting-edge, high-performance, high-speed CMOS ICs in mature foundry nodes (40nm, 55nm, 65nm, 130nm).
• Collaborate with circuit designers to review and analyze floorplans and complex circuits.
• Run full sets of design verification tools for AMS blocks.
• Interpret LVS, DRC, and ERC reports to expedite layout closure.
• Use advanced CAD tools and mask design expertise to ensure layout quality and robustness within strict area, performance, and power requirements.
• Support team leadership by fostering effective communication, organizational structure, delegation, and time management.
• Work with layout leads to plan schedules and negotiating trade-offs.

Preferred Qualifications:

• 10+ years of experience in analog/mixed-signal layout for deep submicron CMOS circuits.
• 3+ years of recent experience in advanced process nodes, including FinFET.
• Strong background in analog/mixed-signal IP (e.g., SERDES PHYs, PLLs, DDR PHYs, ADCs, DACs, LDOs).
• Proven leadership in managing complex layout macros from floorplan to physical verification.
• Deep understanding of CAD flows/tools for analog/mixed-signal layout.
• Proficiency in layout of noise-sensitive, low-power analog blocks (transistors, capacitors, resistors, ESD, etc.).
• Experience with IR drop, RC delay, electro-migration, self-heating, and coupling capacitance issues.
• Skilled in interpreting DRC/LVS/ERC reports via tools like Calibre.
• Proficiency in Cadence or Mentor Graphics layout tools.
• Excellent interpersonal skills and ability to work effectively with remote teams.

Technical Preferences:

• Layout Tools: Synopsys / Cadence / Mentor ( Preference: 5)
• Scripting: Python ( Preference: 3)
• Process Nodes:
• TSMC 7nm or 5nm ( Preference: 3).
• TSMC 3nm ( Preference: 5).