Overview
On Site
$70 - $75
Accepts corp to corp applications
Contract - W2
Contract - 12 Month(s)
No Travel Required
Able to Provide Sponsorship
Skills
ASIC / FPGA
RTL
VHDL
Job Details
Experience range - 6-15 years
Requirements capture, ASIC / FPGA digital architecture and design using RTL, timing closure, verification, and system integration
Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA design flow
Contribute to engineering estimates for new program pursuits.
May provide technical leadership for project design teams by breaking down work, planning activities, and reporting status
Must have Skills:
RTL coding and simulation in VHDL/Veriog
Digital circuit architecture, design, resource tradeoffs, timing analysis and timing closure
Proficiency using ASIC and/or FPGA simulation and synthesis tools (e.g. Modelsim, Synplify, Quartus, Vivado, or other FPGA-specific tools)
Git, Subversion
Experience with Unix, scripting, C/C++, and/or Perl
RTL coding and simulation in VHDL/Veriog
Digital circuit architecture, design, resource tradeoffs, timing analysis and timing closure
Proficiency using ASIC and/or FPGA simulation and synthesis tools (e.g. Modelsim, Synplify, Quartus, Vivado, or other FPGA-specific tools)
Git, Subversion
Experience with Unix, scripting, C/C++, and/or Perl
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