Overview
On Site
Depends on Experience
Full Time
Skills
fpga
validation
Vivado
synthesis
clock
Job Details
- Develop and execute post silicon Validation and Characterization for clocking circuits on in some of the industry s largest and most complex SOCs (using Xilinx s FPGA design tools such as Vivado/ISE).
- Hands-on experience with lab equipment such as oscilloscopes, logic analyzers,Thermosteamer, Clock generators and other equipment.
- Expert knowledge and hands-on experience of the entire backend and adjacent flows, including synthesis, Floor-planning P&R, clocking, timing closure, power, and IO planning
- Working experience of Package level Clock SIPI is a plus.
- Familiarity with Verilog and system Verilog for design is plus.
- Develop test scripts using one of python/tcl/PERL scripting language.
- Analyze data and provide feedback to design teams result will be part of production SW release.
- Document test results and prepare reports for management.
- Strong communication and interpersonal skills.
- Leadership skills for driving cross-functional test plans and debug activities.
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