Overview
On Site
Full Time
Skills
Collaboration
Product Engineering
Bridging
Place And Route
Research and Development
Product Requirements
Electrical Engineering
Computer Engineering
FOCUS
VLSI
Physical Data Model
Timing Closure
Cadence
Verilog
SystemVerilog
Logic Synthesis
Scripting
Perl
Python
Tcl
Shell Scripting
Artificial Intelligence
Analytical Skill
Debugging
Root Cause Analysis
Digital Design
Data Analysis
EDA
Innovation
Job Details
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
We are seeking a highly motivated MS student currently enrolled in a U.S. university for a 3 month internship with our Product Engineering team. This role offers a unique opportunity to work closely with the R&D team on Cadence's industry-leading Genus Synthesis Solution, contributing to the evolution of synthesis and place & route technologies.
Key Responsibilities
Preferred Qualifications
This internship is ideal for students passionate about digital design and EDA, looking to gain hands-on experience in a fast-paced, innovation-driven environment.
We're doing work that matters. Help us solve what others can't.
We are seeking a highly motivated MS student currently enrolled in a U.S. university for a 3 month internship with our Product Engineering team. This role offers a unique opportunity to work closely with the R&D team on Cadence's industry-leading Genus Synthesis Solution, contributing to the evolution of synthesis and place & route technologies.
Key Responsibilities
- Collaborate with the Product Engineering team to evaluate and improve Genus, a logic synthesis tool used to optimize Power, Performance, and Area (PPA) for advanced digital ASICs.
- Analyze and validate new features within Genus, ensuring correctness and identifying optimal configurations.
- Explore and address challenges in physically aware synthesis, bridging the gap between logic synthesis and place & route.
- Support internal teams and customers by troubleshooting tool usage and providing first-line feedback to R&D.
- Contribute to the interoperability of Genus with other Cadence digital implementation tools.
- Assist in documenting Product Requirement Specifications (PRS) for new features based on internal and external feedback.
Preferred Qualifications
- Currently pursuing an MS in Electrical Engineering, ECE or Computer Engineering with a focus on VLSI design.
- Academic or past work experience in EDA, logic synthesis, physical design, or timing closure is a plus.
- Familiarity with Cadence tools such as Genus and Innovus is a plus.
- Exposure to advanced process nodes (7nm and below) through coursework or projects.
- Strong understanding of HDLs (Verilog/SystemVerilog), logic design, and timing analysis.
- Proficiency in scripting languages such as Perl/Python, Tcl, or shell scripting.
- Experience or interest in AI applications and agentic frameworks is a plus.
- Strong analytical and debugging skills, with the ability to perform root-cause analysis and communicate findings effectively.
This internship is ideal for students passionate about digital design and EDA, looking to gain hands-on experience in a fast-paced, innovation-driven environment.
We're doing work that matters. Help us solve what others can't.
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