Tech Lead - FPGA Design Verification

Position -  Tech Lead - FPGA Design Verification

Location: Washington Redmond or Seattle  (Onsite at customer location)
Experience Required: 8–15 years .
Engagement: Long-term | Full-time / Contract
Onsite Requirement: Yes

Role Overview

We are seeking a highly experienced Tech Lead – FPGA Design Verification with strong hands-on expertise in SystemVerilog/UVM and proven leadership capabilities. The ideal candidate will lead verification activities while actively contributing to complex FPGA/ASIC verification projects.

Key Responsibilities

• Lead and manage a Design Verification team of at least 5 engineers
• Design and develop UVM-based verification environments from scratch
• Perform Unit/Module-level design verification
• Integrate and bring up Verification IP (VIP) into UVM testbenches
• Port legacy Verilog/VHDL verification environments to modern UVM-based frameworks
• Create and execute test plans, write coverage models, and perform debugging
• Ensure comprehensive functional and code coverage
• Collaborate closely with design and architecture teams

Required Skills & Experience

• 8+ years of hands-on Design Verification experience
• Strong expertise in SystemVerilog and UVM
• Proven experience building UVM testbenches from scratch
• Deep knowledge of AMBA protocols (AXI, AHB, APB) — mandatory
• Experience with VIP integration and bring-up
• Solid background in test planning, coverage coding, and debugging
• Prior experience leading verification teams (minimum 5 members)
• FPGA and/or ASIC verification experience

Nice to Have

• Experience verifying complex IPs using industry-standard UVM methodologies
• Strong communication and technical leadership skills