Senior Physical Designer

Overview

On Site
Depends on Experience
Contract - W2
No Travel Required

Skills

ASIC
ASIC physical design
physical design
SoC
RTL

Job Details

Triple Crown is a leading provider of hardware, embedded, software, and mechanical engineering talent. Businesses and technology teams, from Fortune 500 enterprises to emerging startups, rely on our ability to rapidly place the developers, architects, coders, and designers who engineer digital transformation and growth.

CONTRACT Position: 6-12 Months

Location: Onsite in Irvine, CA

We are looking for a highly skilled Senior SoC/ASIC Physical Design Engineer to lead and drive all aspects of physical implementation from RTL to GDSII. This role requires deep technical expertise in hierarchical design flows, Fusion Compiler, and Synopsys tools, with a strong focus on achieving best-in-class Power, Performance, and Area (PPA). You will spearhead the development of cutting-edge PD flows and drive physical design execution through to signoff.

  • Develop and Implement PD Flow: Establish a modern physical design (PD) flow utilizing the latest EDA tool fusion and machine learning (ML) techniques to maximize PPA efficiency, optimize resource allocation, and achieve industry-leading time-to-closure and tapeout.
  • End-to-End Physical Design Execution: Perform partition synthesis and physical implementation, including synthesis, floorplanning, power/ground grid generation, place & route, timing, noise, physical verification, electromigration, voltage drop, and signoff checks.
  • Methodology and Automation: Create and refine physical design methodologies and automation scripts to streamline implementation and signoff processes.
  • Cross-Functional Collaboration: Work closely with RTL, DFT, and ASIC design teams to define architectural feasibility, establish timing, power, and area targets, and explore design trade-offs.
  • Drive Design Closure: Utilize an objective, metrics-driven approach to resolve design, timing, and flow issues and ensure predictability in achieving project milestones.
  • Signoff Ownership: Lead signoff closure activities, including static timing analysis (STA), noise analysis, logic equivalency, physical verification, and power integrity (EM/IR).

Requirements:

  • Hierarchical flow, chip level with fusion compiler expertise
  • Strong expertise in Synopsys tools (ICC2, Fusion Compiler, etc.)
  • RTL to GDS implementation

Benefits:

  • Paid weekly!
  • Health, Dental and Vision Insurance
  • 401k
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About Triple Crown Consulting