Design for Test engineer

Overview

Remote
$80 - $100
Contract - W2
Contract - 12 Month(s)

Skills

DFT
cadence
ASIC
VHDL
Verilog

Job Details

Looking for a DFT (Design for Test) engineer to join our highly qualified, diverse individuals as part of our ASIC design team.

What is the technical environment?

Design using Linux platforms

Describe work environment / team culture?

Multi disciplined team of Digital design, Verification and Physical Implementation engineers, many of whom will be working from different sites across USA.

Based on the job description what does a typical day look like?

Develop DFT architecture, provide detailed documentation and work with wider Digital designers to drive the implementation.

What is the training process for this role?

Need someone with prior experience. Expect the DFT expert can ramp up quickly, work with Cadence Application engineers as needed to solve issues as they arise. NG senior engineers will be available to consult with.

Responsibilities:

  • Responsible for DFT (Design for Testability) aspects of ASIC Design thorough understanding of digital design concepts Adhering to Northrop Grumman ASIC development process.
  • Knowledgeable in VHDL, Verilog or System Verilog RTL coding and highly proficient in DFT methodologies.
  • Responsible for operating in a team environment and collaborating across the different teams as required to accomplish the goals.

Basic Qualifications

Bachelor's degree in Electrical or Computer Engineering with 8+ years experience.

  • Bachelor s degree with 8 years of experience, a Master s degree with 6 years of experience U.S. Citizenship is required Experience in full product life cycle of ASIC Design Experience with Cadence and/or Mentor test insertion and ATPG tools Experience with hierarchical scan testing, IEEE-1500 and/or IEEE-1687, test compression, JTAG IEEE-1149.1 and IEEE-1149.6 (AC JTAG) Experience with memory BIST and logic BIST Experience generating test patterns and analyzing and debugging test failures Experience working with test engineers to implement ATPG vectors on tester hardware Proficiency in HDL (VHDL/Verilog/System Verilog) and scripting languages such as Tcl, Python or Perl Effective communication and presentation skills and high proficiency in technical problem solving

Preferred Qualifications:

  • Master's Degree in Electrical or Computer Engineering Expertise of using Cadence Modus DFT tools Knowledge of Synthesis, P&R and Static Timing Analysis would be a plus
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