Low-Latency FPGA Developer HFT Systems, Chicago, IL

Overview

On Site
Depends on Experience
Accepts corp to corp applications
Contract - W2

Skills

FPGA Development
Xilinx UltraScale+
Intel Quartus
PCIe Gen3/Gen4
C++
SERDES

Job Details

Job Title: Low-Latency FPGA Developer HFT Systems
Location: Chicago, IL (100% Onsite)
Type: 6-Month Contract
Experience Level: 12+ Years

Job Description:

A leading high-frequency trading (HFT) firm in Chicago, IL is seeking a Low-Latency FPGA Developer for a 6-month onsite contract role. This opportunity involves developing ultra-low-latency systems on cutting-edge FPGA platforms and collaborating with elite software and hardware teams at the forefront of financial technology innovation.

Key Responsibilities:

  • Design and optimize FPGA firmware (VHDL/Verilog) on Xilinx UltraScale+ or Intel Stratix 10.

  • Work closely with C++ teams to integrate FPGA solutions via PCIe DMA and MMIO for ultra-low-latency trading systems.

  • Build and tune sub-10ns data paths for market feed handlers, order entry, and real-time risk logic.

  • Perform static timing analysis and constraint tuning to meet tight latency budgets.

  • Use Vivado, Quartus, ModelSim, and Mentor Questa for simulation and synthesis.

  • Debug and validate designs using JTAG, logic analyzers, and protocol analyzers.

  • Ensure compliance with MiFID II, SEC, and internal audit standards.

  • Document technical design, testing procedures, and deployment reports.

Required Skills & Experience:

  • 12+ years of FPGA development in HFT, telecom, or embedded real-time systems.

  • Deep expertise in VHDL/Verilog, pipelined architectures, and low-latency design.

  • Expert-level use of Xilinx Vivado and/or Intel Quartus toolchains.

  • Extensive experience with PCIe Gen3/Gen4 DMA and MMIO interfacing.

  • Strong C++ development background (driver, middleware, real-time app integration).

  • Hardware debugging with emulators, JTAG, signal probes, and logic analyzers.

  • Familiar with SERDES, clock domain crossing, and FPGA optimization techniques.

  • Understanding of network protocols: Ethernet, UDP/TCP, FIX, PTP.

  • Bachelor's or Master s in Electrical/Computer Engineering or equivalent.

  • Previous experience in HFT or co-located data center environments is a major plus.

BonPreferred Experience:

  • Familiarity with CXL, HBM2/3, and ultra-high bandwidth interfaces.

  • Experience building tick-to-trade, hardware order books, or market replay systems.

  • Knowledge of multicast normalization, feed timestamping, and cross-asset strategies.

  • Git, Jenkins, Perforce, and agile/hybrid SDLCs in compliance-heavy environments.

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

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