ADVANCED IC PACKAGE DESIGN ENGINEER (COWOS / 2.5D PACKAGING)

Marvell

Santa Clara, CA (Onsite)

6-12 months ongoing (in a perfect world would want a FT conversion)

Manager wants to see people that can fully work onsite

CADENCE ADP is the most important thing, a small write up would go a long way with this manager.

2 interviews, first one with team lead, second one with manager and director (will be a Microsoft Teams video call)

Requirements:

Bachelor s degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience.
Master s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience.

Job Responsibilities:

• Experience with 2.5D package design and development like CoWoS
• Strong expertise in using IC package layout tools like Cadence APD
• Understanding IC package design requirements for high speed interfaces and setup constraints manager
• Interface with the IC physical design teams for optimizing the die floor plan
• Experience in interfacing with Substrate suppliers and OSATs
• Ability to do automation of the layout tasks using scripting
• Power plane design and translating power supply requirements into design
• Familiarity with IC packaging technologies, materials, substrate design rules and assembly rules
• Track record of new product introduction from concept through development and production is a plus
• Knowledge of the thermal and mechanical analysis of the IC package development is a plus
• A team player with strong communication, presentation, and documentation skills