Senior Mask Layout Engineer

Overview

On Site
$60 - $90
Contract - W2
Contract - Independent
Contract - 6 Month(s)

Skills

Mixed - Signal
layout design
FinFET
TSMC
PLL
Serdes

Job Details

Location: San Jose, CA (Must be on-site)

LOA: 6-12 months

Skills: Analog Layout 7nm/5nm FInFET, TSMC, RF, High Speed, PLL, Serdes

Location: San Jose, CA

Analog and Mixed-Signal Layout Engineer

Job Description

The candidate should be able work independently on block level and IP level Analog layout design, coordinating with the circuit designer and the rest of the layout team. The candidate will need to be able to work with both design engineers and mask design engineers in remote locations, and thus the ability to plan and efficiently use email and Webex to review critical aspects of the layout work is essential to this role.

The candidate should have experience with the layout of high-frequency analog and high-speed custom digital circuits in which parasitic minimization is critical.