FPGA Design Verification Engineer

Overview

On Site
Depends on Experience
Full Time
10% Travel

Skills

Degree in Electrical or Computer Engineering
OVM / UVM design verification methodology
FPGA/ASIC design
bash
csh
Perl
TCL
Python
VHDL or similar hardware description languages
Xilinx FPGA & Questa Advanced Functional Verification

Job Details

FPGA Design Verification Engineer (OVM - UVM design verification, FPGA - ASIC design, bash, csh, Perl, TCL, Python, VHDL, Xilinx FPGA & Questa) in Dedham, MA

7+ to 10 years of experience

POSITION: FPGA Design Verification Engineer (OVM - UVM design verification, FPGA - ASIC design, bash, csh, Perl, TCL, Python, VHDL, Xilinx FPGA & Questa) in Dedham, MA
SECURITY CLEARANCE: Must be able to obtain Secret Security Clearance (ship is Required)
LOCATION: Dedham, MA (onsite)
DURATION: Full-Time Position Onsite
SALARY: Excellent Compensation with benefits + relocation + 401K
SKILLS: Degree in Electrical or Computer Engineering, OVM / UVM design verification methodology, FPGA/ASIC design, bash, csh, Perl, TCL, Python, VHDL or similar hardware description languages, Xilinx FPGA & Questa Advanced Functional Verification
DESCRIPTION:

Basic Qualifications:

  • Bachelor s degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 8 years of relevant experience; or
  • Master's degree plus a minimum of 6 years of relevant experience.
  • Experience with OVM, SystemVerilog, UVM design verification methodology: bash/csh, Perl, TCL, Python or similar scripting languages;
  • VHDL or similar hardware description languages.

ROLE AND RESPONSIBILITIES:

  • As a Senior Cyber FPGA Design Verification engineer, you ll be a member of a cross functional team responsible for product design from system architecture & requirements allocation through product release and production of cost-sensitive secure products.
  • Experience defining verification methodology for complex FPGAs.
  • Ability to analyze requirements, create test plan, build and set up scalable simulation environments from the ground up using SystemVerilog/UVM
  • Familiarity with testing complex designs, code coverage, functional coverage, assertions.
  • Ability to work in a dynamic environment that includes working with changing needs and requirements.
  • FPGA/ASIC design experience is a plus.
  • Familiarity with Xilinx FPGA & Questa Advanced Functional Verification tools is a plus.
  • Team player who thrives in collaborative environments and revels in team success

PERKS:

  • Sign on Bonus up to $3000 for New Hires.
  • Opportunities for continuous learning and development.
  • Research oriented work, alongside award winning teams developing practical solutions for our nation s security
  • Flexible schedules with every other Friday off work, if desired (9/80 schedule)
  • Competitive benefits, including 401k matching, flex time off, paid parental leave, healthcare benefits, health & wellness programs, employee resource and social groups, and more

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