Hardware Design Engineer 4

7+ years of experience in RTL synthesis and physical implementation using Synopsys tools (Fusion Compiler, Design Compiler, PrimeTime).
Strong command of RTLA and PrimePower RTL flows, including switching activity modeling and scenario-based analysis.
Proficiency in scripting (TCL, Python) for flow automation and debugging.
Deep understanding of timing constraints, UPF, and low-power design methodologies.
Experience with Linux and bash scripting skills are preferred.
Familiarity with advanced process nodes and associated challenges in timing, congestion, and power closure.
Preferred Qualifications

Experience collaborating with EDA vendors on tool evaluation and runtime profiling.
Exposure to dashboarding and reporting automation for synthesis metrics.
Prior contributions to flow migration or tool benchmarking initiatives.

Top 3 Hard Skills Required + Years of Experience
1. Synthesis (minimum 7 years)
2. Fusion Compiler expertise (minimum 7 years)
3. Prime Power or RTL expertise (minimum 7 years)