Overview
On Site
USD 210,000.00 - 300,000.00 per year
Full Time
Skills
Boost
Collaboration
Integrated Circuit
Failure Analysis
New Product Introduction
NPI
Prototyping
Manufacturing
Semiconductors
2.5D
3D Computer Graphics
Thermal Management
Testing
Analytical Skill
Problem Solving
Conflict Resolution
Mandarin Chinese
English
Electrical Engineering
Materials Science
Mechanical Engineering
Law
Job Details
Piper Companies is seeking a Principal Packaging Engineer who will develop and refine Chip-on-Wafer-on-Substrate technology. The Packaging engineer will be preferred in office in Saratoga, CA, but is open to remote.
Requirements for the Packaging Engineer include:
- Innovate and enhance CoWoS packaging processes to boost chip performance, power efficiency, and reliability.
- Collaborate with design, test, and manufacturing teams to ensure flawless chip-package integration.
- Lead failure analysis and drive yield improvements across packaging processes.
- Ensure CoWoS packaging meets all thermal, mechanical, and electrical performance standards.
- Support new product introduction (NPI) from initial prototyping to high-volume manufacturing.
- Partner with foundry and OSAT partners (e.g., TSMC, ASE, Amkor, SPIL) on process qualification and production ramp-up.
Qualifications for the Packaging Engineer include:
- 15 years of hands-on experience in advanced semiconductor packaging and interconnect processes.
- Proven expertise in CoWoS / FOCoS (highly preferred), or FOWLP; familiarity with EMIB, InFO, and advanced 2.5D/3D integration technologies is a plus.
- Strong knowledge of thermal management, reliability testing, and signal/power integrity challenges.
- Excellent analytical and problem-solving skills with a proactive and collaborative mindset.
- Experience working with TSMC and leading OSATs.
- Proficiency in Mandarin and English is preferred.
- Bachelor's or Master's degree in Electrical Engineering, Materials Science, Mechanical Engineering, or a related field.
Compensation for the Packaging Engineer includes:
- Salary range: $210,000 - $300,000
- Comprehensive benefit package: Medical, Dental, Vision, 401k match plus PTO, Sick leave as required by law, and Paid Holidays
Requirements for the Packaging Engineer include:
- Innovate and enhance CoWoS packaging processes to boost chip performance, power efficiency, and reliability.
- Collaborate with design, test, and manufacturing teams to ensure flawless chip-package integration.
- Lead failure analysis and drive yield improvements across packaging processes.
- Ensure CoWoS packaging meets all thermal, mechanical, and electrical performance standards.
- Support new product introduction (NPI) from initial prototyping to high-volume manufacturing.
- Partner with foundry and OSAT partners (e.g., TSMC, ASE, Amkor, SPIL) on process qualification and production ramp-up.
Qualifications for the Packaging Engineer include:
- 15 years of hands-on experience in advanced semiconductor packaging and interconnect processes.
- Proven expertise in CoWoS / FOCoS (highly preferred), or FOWLP; familiarity with EMIB, InFO, and advanced 2.5D/3D integration technologies is a plus.
- Strong knowledge of thermal management, reliability testing, and signal/power integrity challenges.
- Excellent analytical and problem-solving skills with a proactive and collaborative mindset.
- Experience working with TSMC and leading OSATs.
- Proficiency in Mandarin and English is preferred.
- Bachelor's or Master's degree in Electrical Engineering, Materials Science, Mechanical Engineering, or a related field.
Compensation for the Packaging Engineer includes:
- Salary range: $210,000 - $300,000
- Comprehensive benefit package: Medical, Dental, Vision, 401k match plus PTO, Sick leave as required by law, and Paid Holidays
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