Memory PHY RTL design Engineer at Boxborough, MA

Role Title: Memory PHY RTL Design Engineer

Location: Boxborough, MA (Hybrid - 3 days a week)

Duration: 12+ months contract

THE ROLE:

The Memory PHY team is looking for a passionate and experienced Design Engineer for RTL and Firmware development of high-speed LPDDR, DDR IPs. Be a part of the definition, design and development phase of industry-leading Memory PHYs and interface IP. This opportunity includes creation of new IO designs as well as working on multiple designs and enhancing methodologies in parallel. Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit, and architecture teams develop leading edge and differentiating IPs.

THE PERSON:

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES:

RTL design for memory I/O

PHY Digital Architecture development from pathfinding, coding, verification to physical implementation

PHY link layer design, implementation & verification with Analog and System architect.

PHY Analog/Digital co-design

Digital design and RTL coding

Timing Synthesis & Drive Physical implementation

Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified

Build the unit tests

Debug design failures to determine the root cause; work with DV and firmware engineers to resolve design defects and correct any test issues

PREFERRED EXPERIENCE:

Digital design engineering experience

Proficient in debugging firmware and RTL code using simulation tools

Proficient in using UVM testbenches and working in Linux and Windows environments

Experienced with Verilog, System Verilog, C, and C++

Excellent knowledge of Verilog, System Verilog and a scripting language; experience with Python, Perl and TCL is a plus

Knowledge of clocking architectures, synchronization, and CDC methodology

SERDES, DDR, Memory Controller, or MAC Design experience is preferred

Strong understanding of computer organization/architecture.

Mixed signal RTL experience is a plus

ACADEMIC CREDENTIALS:

Bachelors or Masters degree in computer engineering/Electrical Engineering