Overview
On Site
$50 to 65 per hour
Accepts corp to corp applications
Contract - W2
Contract - 9 month(s)
Skills
Design Verification
UVM
mixed-signal
Job Details
Title: Mixed-Signal Design Verification Engineer
Location: San Jose, CA
Key Technical Skills:UVM/System Verilog, Python, Synopsys/Cadence EDA Verifications Tools, AMS Verification
Required Experience/Skills:
Location: San Jose, CA
Key Technical Skills:UVM/System Verilog, Python, Synopsys/Cadence EDA Verifications Tools, AMS Verification
Required Experience/Skills:
Good knowledge of System-Verilog RTL coding including state machines, adders, multipliers, combinatorial logic, etc.
Good understanding of digital design for mixed signal control loops and designing Verilog / Verilog- A code to control analog circuits (e.g. bandgap, PLL, Amplifier, Filters, CDR.,)
Familiarity with behavioral Verilog code for an analog circuit
Ability to write thorough test benches for digital and AMS simulators
Deep understanding of constraints, especially for mixed-signal designs, including multiple clock domains and clock gating
Familiarity with timing closure and static timing analysis tools
Experience with scan chain vector generation and verification
Good understanding of digital design for mixed signal control loops and designing Verilog / Verilog- A code to control analog circuits (e.g. bandgap, PLL, Amplifier, Filters, CDR.,)
Familiarity with behavioral Verilog code for an analog circuit
Ability to write thorough test benches for digital and AMS simulators
Deep understanding of constraints, especially for mixed-signal designs, including multiple clock domains and clock gating
Familiarity with timing closure and static timing analysis tools
Experience with scan chain vector generation and verification
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