Overview
On Site
$60 - $70
Contract - W2
Contract - 12 Month(s)
No Travel Required
Skills
ASIC
Synopsys
SystemVerilog
Tcl
Static Timing Analysis
Python
Physical Data Model
Integrated Circuit
Formal Verification
Verilog
Job Details
About the Role:
Seeking an experienced STA/SDC engineer to own block and full-chip constraints, perform Static Timing Analysis (PrimeTime/Tempus), and collaborate with design and physical design teams for timing closure.
Key Skills:
Strong expertise in STA and SDC constraints (functional & test modes)
Experience with PrimeTime, Tempus, and synthesis tools (Synopsys DC/DCG/FC)
Verilog/SystemVerilog design knowledge
CDC/glitch analysis (Spyglass CDC), Formal Verification (Formality, LEC)
Scripting experience (Python, Perl, or TCL)
Ability to bridge design and physical design teams
Qualifications:
B.S. in EE/CE with 7+ years, or M.S. with 5+ years of ASIC design or related experience
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