Overview
On Site
Hybrid
USD 78.35 per hour
Full Time
Skills
Science
Radio
calibre
Cadence
Communication
Scripting
Perl
Integrated Circuit
IC
Internal Communications
Research
Wireless Communication
CMOS
Analog Circuits
Extraction
LVS
Design For Manufacturability
Routing
IQ
Mixed-signal Integrated Circuit
Crystal Reports
User Experience
VLSI
RTL
Emulation
Layout
RF
Intellectual Property
IP
System On A Chip
Art
Job Details
Date Posted: 08/08/2025
Hiring Organization: Rose International
Position Number: 486705
Industry: IT Company
Job Title: Mask Layout Designer
Job Location: Cupertino, CA, USA, 95014
Work Model: Hybrid
Work Model Details: Hybrid- 3 days Onsite
Shift: 9 AM - 6 PM
Employment Type: Temporary
FT/PT: Full-Time
Estimated Duration (In months): 7
Min Hourly Rate($): 78.35
Max Hourly Rate($): 78.35
Must Have Skills/Attributes: Design, iOS, Layout
Experience Desired: FinFet Technology , Mask Layout design, RF/analog layout (5 yrs); RC delay, electro migration, and coupling, CADENCE layout tools (2 yrs)
Required Minimum Education: Bachelor's Degree
**C2C is not available**
Job Description
Education: Bachelor of Science or Bachelor of Engineering
Skills:
5 + Years of experience with FinFet Technology
Experience in custom RF/analog layout for radio transceivers with extensive knowledge of deep sub-micron CMOS.
Knowledgeable in layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing.
Solid understanding of RC delay, electromigration, and coupling.
Understanding of guard rings, DNW, PN junctions, and advanced process effects such as LOD, WPE, etc.
High level proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc. in FinFet Technology (7nm experience highly preferred)
Knowledge of CADENCE layout tools.
Excellent communication skills and able to work with cross-functional teams.
Scripting skills in PERL or SKILL are a plus, but not required.
Responsibilities:
As an IC Layout Engineer, you will be a key member of our team, researching, designing and bringing the next-generation of wireless technologies into high-volume production in advanced CMOS technology nodes.
Responsibilities include: - Detailed transistor-level layout of RF and analog circuit blocks including LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC/DAC, baseband filters, and bandgap/bias/LDO. - Block level layout through full verification flow including extraction, DRC, LVS, and DFM checking. - Co-work with designers on block level floorplanning. - Layout review for power/gnd routing, electromigration, signal path check, differential and IQ matching, and signal coupling.
Summary
Our teams are responsible for the design of a wide range of RF, analog, and mixed-signal blocks from RF front-end amplifiers to data converters, including baseband filters, baseband and RF phase-locked loops, crystal oscillators, and bandgap references.
We are working on new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering.
In this role, you will work closely with the design team to layout and verify custom RF and analog IP for complex SoC products.
You will have a critical impact on developing Client's state-of-the-art designs and getting them into hundreds of millions of products.
Benefits:
For information and details on employment benefits offered with this position, please visit here. Should you have any questions/concerns, please contact our HR Department via our secure website.
California Pay Equity:
For information and details on pay equity laws in California, please visit the State of California Department of Industrial Relations' website here.
Rose International is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender (expression or identity), national origin, arrest and conviction records, disability, veteran status or any other characteristic protected by law. Positions located in San Francisco and Los Angeles, California will be administered in accordance with their respective Fair Chance Ordinances.
If you need assistance in completing this application, or during any phase of the application, interview, hiring, or employment process, whether due to a disability or otherwise, please contact our HR Department.
Rose International has an official agreement (ID #132522), effective June 30, 2008, with the U.S. Department of Homeland Security, U.S. Citizenship and Immigration Services, Employment Verification Program (E-Verify). (Posting required by OCGA 13/10-91.).
Hiring Organization: Rose International
Position Number: 486705
Industry: IT Company
Job Title: Mask Layout Designer
Job Location: Cupertino, CA, USA, 95014
Work Model: Hybrid
Work Model Details: Hybrid- 3 days Onsite
Shift: 9 AM - 6 PM
Employment Type: Temporary
FT/PT: Full-Time
Estimated Duration (In months): 7
Min Hourly Rate($): 78.35
Max Hourly Rate($): 78.35
Must Have Skills/Attributes: Design, iOS, Layout
Experience Desired: FinFet Technology , Mask Layout design, RF/analog layout (5 yrs); RC delay, electro migration, and coupling, CADENCE layout tools (2 yrs)
Required Minimum Education: Bachelor's Degree
**C2C is not available**
Job Description
Education: Bachelor of Science or Bachelor of Engineering
Skills:
5 + Years of experience with FinFet Technology
Experience in custom RF/analog layout for radio transceivers with extensive knowledge of deep sub-micron CMOS.
Knowledgeable in layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing.
Solid understanding of RC delay, electromigration, and coupling.
Understanding of guard rings, DNW, PN junctions, and advanced process effects such as LOD, WPE, etc.
High level proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc. in FinFet Technology (7nm experience highly preferred)
Knowledge of CADENCE layout tools.
Excellent communication skills and able to work with cross-functional teams.
Scripting skills in PERL or SKILL are a plus, but not required.
Responsibilities:
As an IC Layout Engineer, you will be a key member of our team, researching, designing and bringing the next-generation of wireless technologies into high-volume production in advanced CMOS technology nodes.
Responsibilities include: - Detailed transistor-level layout of RF and analog circuit blocks including LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC/DAC, baseband filters, and bandgap/bias/LDO. - Block level layout through full verification flow including extraction, DRC, LVS, and DFM checking. - Co-work with designers on block level floorplanning. - Layout review for power/gnd routing, electromigration, signal path check, differential and IQ matching, and signal coupling.
Summary
Our teams are responsible for the design of a wide range of RF, analog, and mixed-signal blocks from RF front-end amplifiers to data converters, including baseband filters, baseband and RF phase-locked loops, crystal oscillators, and bandgap references.
We are working on new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering.
In this role, you will work closely with the design team to layout and verify custom RF and analog IP for complex SoC products.
You will have a critical impact on developing Client's state-of-the-art designs and getting them into hundreds of millions of products.
- **Only those lawfully authorized to work in the designated country associated with the position will be considered.**
- **Please note that all Position start dates and duration are estimates and may be reduced or lengthened based upon a client's business needs and requirements.**
Benefits:
For information and details on employment benefits offered with this position, please visit here. Should you have any questions/concerns, please contact our HR Department via our secure website.
California Pay Equity:
For information and details on pay equity laws in California, please visit the State of California Department of Industrial Relations' website here.
Rose International is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender (expression or identity), national origin, arrest and conviction records, disability, veteran status or any other characteristic protected by law. Positions located in San Francisco and Los Angeles, California will be administered in accordance with their respective Fair Chance Ordinances.
If you need assistance in completing this application, or during any phase of the application, interview, hiring, or employment process, whether due to a disability or otherwise, please contact our HR Department.
Rose International has an official agreement (ID #132522), effective June 30, 2008, with the U.S. Department of Homeland Security, U.S. Citizenship and Immigration Services, Employment Verification Program (E-Verify). (Posting required by OCGA 13/10-91.).
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.