Manager, of FPGA Design

RESPONSIBILITIES:
Kforce has a client that is seeking a Manager of Digital FPGA Design in Mesa, AZ. We are working directly with the Hiring Manager on this search assignment. The company offers a competitive compensation package including base salary and profit sharing.

Responsibilities:
* The Manager of Digital FPGA Design will manage a matrixed team of up to 10-12
* Provide technical support and knowledge
* Select engineering tools
* Drive improvements in design processes
* Mentor and encourage new engineers
* Lead fault analysis team
* Allocate engineering personnel
* Review circuit analysis and board level designs
* Ensuring engineering team adheres to the required policies and processes
* As a Manager of Digital FPGA Design, you will foster a culture of enjoying engineering design
* Review electrical schematics/layouts
* Review FPGA designs
* Attend design reviews
* Provide engineering feedback to design architectures
* Encourage teamwork
* Provide team members the correct tools for the job
* Measure and report progress toward on-time delivery goals
* The Manager of FPGA Design will ensure the design project meets internal and customer requirements by ensuring adherence to the required policies and procedures

REQUIREMENTS:
* Bachelor's degree in Electrical Engineering, Computer Engineering, Physics, Aerospace Engineering or similar field
* At least 8-10+ years of previous design and development in FPGA design or similar technologies
* Experience leading and managing a team of Design Engineers
* Strong experience in VHDL and/or Verilog coding and how to optimize for performance
* Digital design experience in some of the following would be ideal or similar: modern microprocessors/DSPs, high speed digital logic, FPGA, memory, analog-to-digital, digital-to-analog converters, and communication links
* Knowledge of board design and layout including design tools is a plus but not required
* Experience in regulated industries such as Medical Device, Aerospace, Consumer Electronics, Semiconductor or similar would be ideal
* Previous experience in power dissipation, power use, timing, signal integrity, component derating, and Acceptance Test/Built-In Test coverage is preferred
* Analysis experience including power dissipation, power consumption, timing, signal integrity, component derating would be a plus
* Previous experience designing test benches and simulations using digital simulation tools (example ModelSim, Active-HDL) for verification of FPGA designs is a plus

The pay range is the lowest to highest compensation we reasonably in good faith believe we would pay at posting for this role. We may ultimately pay more or less than this range. Employee pay is based on factors like relevant education, qualifications, certifications, experience, skills, seniority, location, performance, union contract and business needs. This range may be modified in the future.

We offer comprehensive benefits including medical/dental/vision insurance, HSA, FSA, 401(k), and life, disability & ADD insurance to eligible employees. Salaried personnel receive paid time off. Hourly employees are not eligible for paid time off unless required by law. Hourly employees on a Service Contract Act project are eligible for paid sick leave.

Note: Pay is not considered compensation until it is earned, vested and determinable. The amount and availability of any compensation remains in Kforce's sole discretion unless and until paid and may be modified in its discretion consistent with the law.

This job is not eligible for bonuses, incentives or commissions.

Kforce is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, pregnancy, sexual orientation, gender identity, national origin, age, protected veteran status, or disability status.