Overview
On Site
$50 - $60
Contract - W2
Contract - 12 Month(s)
Skills
SAP Treasury
SAP Transaction Manager
Analog Circuit Design
SerDes Design
Serializer/Deserializer
Phase-Locked Loop (PLL)
ADC / DAC Design
Modulator Drivers
ESD Protection Circuits
Mixed-Signal Verification Flows
28Gbps
Cadence Virtuoso
Calibre (DRC/LVS/PEX)
Layout Versus Schematic (LVS)
Design Rule Check (DRC)
EM/IR Sign-Off
Job Details
Role 1: Job Description: Circuit Design Analog Designer
Minimum Qualifications
The ideal candidate should have a minimum of MS in Electrical Engineering with 8+ years of experience in high-speed serial links and deep knowledge of analog CMOS/BiCMOS designs in deep sub-micron process technologies.
- Hands-on circuit design experience of SerDes blocks like Equalizers, PLL, Phase-Interpolators, CDR, etc. for 28Gbps+ data rates
- Experience with design of inductors, transmission line, Trans-Impedance Amplifiers (TIA) and modulator drivers
- Experience with the design of precision analog circuits like ADC/DACs
- Experience with Mixed signal design/verification flows
- Experience with full-chip designs, ESDs and verification flows
Excellent oral and written communication skills
OR
Role 2: Job Description: Analog Layout Engineer
The ideal candidate should have a minimum of BS/MS in Electrical Engineering with 8+ years of experience in high-speed/precision analog layout designs in deep sub-micron process technologies (FinFET).
- Experience in industry standard mask design/verification tools (Cadence/Synopsys, Calibre)
- Hands-on custom layout design experience of high-speed SerDes blocks like Equalizers, PLL, Phase-Interpolators, CDR, etc.
- Hands-on custom layout design experience of precision analog blocks like ADCs/DACs
- Experience in floor planning, closing design sign-off with multiple rails/ESDs
- Experience in integration of digital hard IPs
- Experience in efficient DRC debugging, SKILL coding
- Excellent oral and written communication skills
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