Overview
On Site
Hybrid
BASED ON EXPERIENCE
Contract - W2
Skills
FPGA/ASIC DESIGN ENGINEER
VHDL
VERILOG
SYSTEMVERILOG
DO-254
TCL
DESIGN ENGINEER
Job Details
DPP is seeking an FPGA/ASIC Design Engineer for an opportunity in Indianapolis, Indiana.
Work arrangement:
Click the apply button or contact our recruiter Carolyn at to learn more about this position (#25-00602). EOE/AA/V/D
Work arrangement:
- Onsite; 25% travel between sites (Indianapolis and West Lafayette, IN) as needed for work
- W2 position; 12 months
- Candidates must have ship
- In this technical role, the Design Engineer will design, verify, integrate, and test FPGA/ASIC solutions, which will be integrated into current and future engine control system products.
- You will be responsible for developing FPGA/ASIC architectures, coding, running simulations, synthesis, creating test benches, and preparing documentation to be reviewed by certification authorities.
- This is an exciting opportunity to work closely with world class hardware and software engineers during planning, generating requirements, developing FPGA/ASIC architectures, designing, and testing custom FPGA/ASIC implementations, and system integration phases.
- Participate in all phases of project, to produce detailed design documentation, verification plans and reports.
- The design and development of all custom digital devices (ASIC or FPGA), to support electronic engine control units.
- The verification of complex products that use FPGAs and/or ASICs to DO-254.
- Develop RTL utilizing a hardware description language (e.g. VHDL, Verilog, and/or SystemVerilog) and debug the design via simulation tools.
- Expertise achieving timing closure on FPGA designs and generating test benches.
- Evaluate the process flow including but not limited to high level design, synthesis, place and route, timing constraints and power utilization.
- Bachelor's degree in Electronics Engineering and/or Computer Engineering with 5+ years of experience,
- OR, Master's degree in Electronics Engineering and/or Computer Engineering,
- OR, JD/PhD
- Validate the FPGA hardware in the lab using test equipment (oscilloscopes, logic analyzers) and debug tools (e.g., ILA, JTAG)
- Experience in scripting with languages such as TCL, Python, Shell scripts.
- Able to work with Windows and Linux development environment.
- Demonstrable experience in version control, such as Git, SVN.
- Experience of Actel & Xilinx tool flows to implement complete designs.
Click the apply button or contact our recruiter Carolyn at to learn more about this position (#25-00602). EOE/AA/V/D
DPP offers a range of compensation and benefits packages to our employees and their eligible dependents. Call today to learn more about working with DPP.
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.