Overview
On Site
Full Time
Skills
Timing closure
Signal integrity
Design review
Design
Integrated circuit
System on a chip
Static timing analysis
Data Analysis
Management
Debugging
ICC
Electronic data interchange
Planning
Software development
Python
Perl
Tcl
Simulation
Scripting
Scheduling
Delegation
Job Details
Summary
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, you and your team will enable our customers to do all the things they love with their devices!The Signoff Engineer ensures that all critical, necessary, and appropriate verification and analysis work has been performed on a design before tapeout. This high-visibility position is responsible for the definition, development, and implementation of signoff requirements for PNR construction flows, and analysis for STA, Noise, and Clocks of high-volume SOC. We work closely with other teams in the organization to verify that the EDA flows and tools are set up and run correctly during the project, and all signoff criteria are met at the end of the project. This role also requires direct interaction with technology, CAD, and design groups to provide frontline support for enablement, enhancement, and debug requests.
Key Qualifications
We are looking for: Knowledge of PNR design flowsExperience with PNR tools such as ICC, EDI, Primetime, TempusGood understanding of STA and Noise analysis flowsExperience in timing closure, clock tree construction, and signal integrityPreferably having experience in synthesis, floor planning, placement, and routingProficient in programming using Python, Perl and Tcl
Description
- Determine signoff criteria for PNR design, STA, Signal Integrity, and Clock construction / simulation- Work closely with PNR design, CAD, Technology, and Power teams- Participate in technology and design reviews- Develop and maintain signoff checks- Develop and maintain scripts for signoff verification- Resolve signoff timing requirements across all modes and corners- Verification of CAD flows- Drive signoff reviews with design teams- Enable design teams for signoff milestones and signoff scheduling. Signature delegation and tracking .- Ability to work in a demanding, team-oriented environment- Support and debug signoff flow issues
Education & Experience
Minimum requirement of BS + 3 years of relevant industry experience
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, you and your team will enable our customers to do all the things they love with their devices!The Signoff Engineer ensures that all critical, necessary, and appropriate verification and analysis work has been performed on a design before tapeout. This high-visibility position is responsible for the definition, development, and implementation of signoff requirements for PNR construction flows, and analysis for STA, Noise, and Clocks of high-volume SOC. We work closely with other teams in the organization to verify that the EDA flows and tools are set up and run correctly during the project, and all signoff criteria are met at the end of the project. This role also requires direct interaction with technology, CAD, and design groups to provide frontline support for enablement, enhancement, and debug requests.
Key Qualifications
We are looking for: Knowledge of PNR design flowsExperience with PNR tools such as ICC, EDI, Primetime, TempusGood understanding of STA and Noise analysis flowsExperience in timing closure, clock tree construction, and signal integrityPreferably having experience in synthesis, floor planning, placement, and routingProficient in programming using Python, Perl and Tcl
Description
- Determine signoff criteria for PNR design, STA, Signal Integrity, and Clock construction / simulation- Work closely with PNR design, CAD, Technology, and Power teams- Participate in technology and design reviews- Develop and maintain signoff checks- Develop and maintain scripts for signoff verification- Resolve signoff timing requirements across all modes and corners- Verification of CAD flows- Drive signoff reviews with design teams- Enable design teams for signoff milestones and signoff scheduling. Signature delegation and tracking .- Ability to work in a demanding, team-oriented environment- Support and debug signoff flow issues
Education & Experience
Minimum requirement of BS + 3 years of relevant industry experience