Overview
Remote
$80 - $100
Full Time
Skills
UVM
SystemVerilog
Job Details
Key Responsibilities:
- Develop and maintain SystemVerilog/UVM-based testbenches for complex digital designs.
- Create and execute detailed test plans covering directed and constrained-random scenarios.
- Apply Object-Oriented Design principles to build scalable and reusable verification components.
- Analyze and improve code coverage metrics to ensure thorough verification.
- Write and maintain scripts (e.g., Python, Perl, Tcl) to automate verification flows and data analysis.
- Understand and enhance existing testbench infrastructure to improve efficiency and coverage.
- Collaborate with design engineers to comprehend custom logic and propose effective verification strategies.
- Fuse Controller testing in both in-system and manufacturing environments.
- Debug and resolve issues found during simulation and regression testing.
- Utilize industry-standard simulators such as XLM and Verdi for waveform analysis, debugging, and verification.
Required Skills & Qualifications:
- Proven experience with SystemVerilog and UVM methodology.
- Strong understanding of verification planning, including test case development and coverage analysis.
- Proficiency in Object-Oriented Programming concepts.
- Experience with functional and code coverage tools (e.g., VCS, Questa, Synopsys VC).
- Familiarity with scripting languages such as Python, Perl, or Tcl.
- Hands-on experience with XLM and Verdi simulators.
- Solid understanding of Fuse Controller architecture and behavior
- Excellent problem-solving and communication skills.
- Ability to work independently and in cross-functional teams.
- Experience with JTAG expected, including ICL
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