Static Timing Analysis Engineer OR STA Engineer

  • Posted 60+ days ago | Updated 5 days ago

Overview

Remote
Depends on Experience
Accepts corp to corp applications
Contract - Independent
Contract - W2
Contract - 12 Month(s)

Skills

Timing
STA
CHIP
SOC
ASIC

Job Details

 

Skill (Design Track)

0 to 10 (0 lowest, 10 highest)

RTL development/SOC Integration

 

Lint run, analysis and reporting

 

CDC run, analysis and reporting

 

RDC run, analysis and reporting

 

DFT Architecture

 

Timing Constraints Development for Synthesis

 

Synthesis

 

Power / UPF / formal Structural Checks (VCLP)

 

FEV/LEC

 

VCLP

 

Power Estimation

 

UPF file Editing

 

 

 

 

Requirement

Skill Set

 

Location

JD

Implementation

Power/UPF

 

Remote

Role Description:

Contribute to micro-architecture specification for SoC design block
Participated in 2-3 SoC projects
Participate in SoC Chip Architecture specification reviews
Must have extensive experience in Micro-architecture design for SoC sub-blocks
Interact with SoC integration, verification, and physical design teams and also with IP vendors
Extensive experience in SoC RTL coding (Verilog or System-Verilog). Experience in RTL Code Linting and CDC checks.
Experience in RTL integration using Industry standard tools, is an added advantage
Handle complete responsibility of an entire block starting from Micro-architecture specifications, RTL implementation, Linting, CDC, Synthesis/STA
Experience in low power design techniques
Good understanding of DFx design techniques
Good appreciation of AXI/AHB bus protocol, GigBE, USB, NAND Flash Technology, PCIe Gen2/3 Host interface, DDR2/3 memory interfaces etc.
Experience in PCIe, HBM memory protocol is Preferred

Timing Constraints/Synthesis  needs to develop timing constrain from Scratch

FEC/LEC

 

 

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