Overview
On Site
$50 - $70
Contract - Independent
Contract - W2
Contract - 1 Year(s)
Skills
ARM
C++
DDR SDRAM
JTAG
JEDEC
Python
Electronics
Firmware
System On A Chip
Test Plans
Perl
Computer Hardware
C
Job Details
PSV DDR Validation Engineer
- Take lead responsibility for validating DDR memory subsystems (LPDDR4x, LPDDR5x) on multiple SoC platforms.
- Define comprehensive test plans and execute tests covering memory training procedures, performance benchmarks, stress scenarios, timing margin analysis, and overall reliability.
- Collaborate with design and firmware teams to develop, integrate, and debug firmware essential for memory training. Write necessary firmware components (like bootloaders, memory drivers, test hooks) to enable testing.
- Integrate and debug firmware for memory initialization and training, specifically on systems using RISC-V or ARM processors.
- Work closely with software and hardware teams to ensure firmware and hardware components interact correctly. Coordinate with board and Signal/Power Integrity (SI/PI) teams for related evaluations.
- Utilize standard lab equipment (oscilloscopes, logic analyzers, BERTs, power analyzers) for test execution, data collection, and troubleshooting memory-related issues. Perform root cause analysis for failures.
- Develop scripts (Python, Perl, C/C++) to automate test procedures and validation workflows.
Key skills - DDR, LPDDR4x, LPDDR5x, SOC, RISC-V, ARM, Python, Perl, C/C++), oscilloscopes, logic analyzers, BERTs, power analyzers, Lauterbach, JTAG, JEDEC LPDDR
B.E/M. E in Electronics & Communication Engineering
Regards
Rohit
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