Overview
On Site
Depends on Experience
Full Time
Skills
CAD
TCL
Perl
Python
Job Details
Position: ASIC STA Engineer
Location: Maynard, MA (Onsite)
Job Description
We are looking for a senior ASIC STA Engineer to handle full-chip timing analysis, closure, and design guidance for next-gen 100G 1T optical communication ASICs in a collaborative team.
We are looking for a senior ASIC STA Engineer to handle full-chip timing analysis, closure, and design guidance for next-gen 100G 1T optical communication ASICs in a collaborative team.
Qualifications:
Key Essential Functions
- Professional engineering experience, including experience in advanced technology nodes: 16nm and below
- Familiar with industry standard CAD methodologies from Cadence and/or Synopsys
- Good scripting skills with TCL and either Perl or Python
- Solid analytical, communication and presentation skills
Key Essential Functions
- Involved in static timing analysis (STA) methodology and flow. Including but not limited to latest timing technologies, like latest on-chip variation modeling techniques, PVT selection, extraction methodology and flow, etc.
- Run signoff timing analysis at the top level, drive closure of timing across the team. Interface with EDA vendors on issues/features/enhancements on timing tools.
- Work closely with RTL designers to debug and root-cause timing issues related to design, tools, etc. and arrive at a feasible solution through the augmentation of input and design collateral.
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