Digital SerDes Architect - Remote (Local to Texas only)

Digital SerDes Architect - Remote (Local to Texas only)

Local to Texas Travel required to Santa Clara whenever needed

Full time

This position allows candidates to work remotely from Texas. However, candidates must be available to travel to the Santa Clara, CA office for work whenever necessary.

Role Description

Iitjobs is seeking a Digital SerDes Architect with 8+ years of experience in digital design and architecture for high-speed PHYs. The candidate will define the digital architecture, clocking schemes, and protocol integration for SerDes IPs, collaborating across analog and system domains to deliver robust, scalable designs.

Key Responsibilities

• Define and develop digital architecture for SerDes PHYs (PCS, adaptation, calibration logic, DFT).
• Implement RTL for critical digital sub-blocks and oversee synthesis/STA sign-off.
• Develop behavioral models (Verilog-A/AMS/SystemVerilog) for system-level validation.
• Drive digital verification strategy (UVM, assertions, coverage).
• Collaborate with analog and package teams to ensure seamless integration.
• Support post-silicon debug, firmware development, and system-level testing.

Qualifications

• 8+ years of hands-on digital design/architecture in SerDes or high-speed IP.
• Strong background in RTL coding, synthesis, STA, and low-power design techniques.
• Knowledge of protocol standards (PCIe Gen5/6, UCIe, CXL, Ethernet, DDR).
• Familiarity with DFT, calibration algorithms, and adaptation logic.
• Proficiency in UVM/verification environments.
• MS/PhD in Electrical or Computer Engineering (preferred).