Hardware Infrastructure Development Engineer

Job Title: - Hardware Infrastructure Development Engineer

Job location: - Sunnyvale, CA

Workplace type: - Hybrid

Employment type: - 12+ Months Contract

Job Description: -

As a Senior Software Engineer V on the Hardware Testing Infrastructure team, we are looking for a key player in defining the testing approach, creating the necessary resources, and fostering a culture of quality within our ASIC team. Your primary focus will be on hands-on software development, automation, and ensuring that our ASIC developers have the tools and infrastructure needed to excel in their roles.

Key Responsibilities:

• Define and implement the testing approach for custom chips designed by our ASIC team.
• Develop and maintain testing infrastructure, including disk space and compute capacity management.
• Implement monitoring, reporting, and metrics collection to track the quality, performance, and utilization of testing infrastructure.
• Collaborate with ASIC developers to automate testing and ensure continuous integration and delivery.
• Drive a culture of quality, evidence-driven debugging/triage, root cause analysis, and test-driven development within the team.
• Utilize Python, Jinja2/Templating engines, Make/CMake, Bazel/Blaze/Buck build tools, Git/Mercurial, YAML, JSON, and other relevant technologies for software development.
• Develop and maintain automated dashboards that provide real-time visibility into the team s progress, including work remaining, work completed, change fail rate, lead time for changes, time to recover test failures, and other key performance metrics, ensuring transparency and accountability across the organization.
• Make a significant impact on the world of AI and machine learning by ensuring the quality of our custom chips.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical Engineering, or equivalent experience.
• Minimum of 5 years of software development experience.
• Proficiency in Python and experience with build tools like Make/CMake, Bazel/Blaze/Buck.
• Strong knowledge of version control systems such as Git/Mercurial.
• Familiarity with YAML and JSON for configuration and data exchange.
• Proven experience in evidence-driven debugging, root cause analysis, and test-driven development.

Preferred Experience:

• C++/Rust Proficiency: Strong proficiency in C++/Rust programming is highly desired. Experience in developing software components for hardware modeling and simulation in C++ will be a significant asset.
• Hardware Modeling: Familiarity with hardware modeling concepts, including the ability to work with hardware description languages (e.g., Verilog), is a plus. Understanding the intricacies of hardware design and modeling will be beneficial in this role.
• Hardware Simulators: Prior experience with hardware simulators such as Imperas and QEMU is preferred. Proficiency in configuring, extending, and optimizing these simulators for specific testing scenarios is a valuable skill.
• Verilog Tools and Compilation Flows: Knowledge of Verilog tools and compilation flows is advantageous. Experience in using these tools to analyze, debug, and optimize hardware designs will contribute to the success of the team.
• AI Frameworks: Familiarity with popular AI frameworks like PyTorch, TensorFlow, Caffe2, and others is a plus. Understanding how these frameworks interact with custom hardware and the ability to integrate them into the testing infrastructure will be beneficial.