ASIC/RTL Design Engineer - Onsite

  • San Jose, CA
  • Posted 14 hours ago | Updated 14 hours ago

Overview

On Site
$73.57 - $78.57
Contract - W2
Contract - 6 Month(s)

Skills

CAD tools
synthesis
lint
CDC
RDC
PrimeTime
IP
ARM cores
Ethernet
DDR
DMA
PCIE
SATA
SoC
SoC design
Chip definition
Architecture development and modeling
RTL Design
ASIC design flow
IP Integration
debugging
verification
physical execution
software
silicon bring-up
I/O interface
micro architectural specifications
logic implementation
emulation
debug

Job Details

Title: ASIC/RTL Design Engineer - Onsite

Description:

Top skills:

RTL coding, TCL coding, Python coding, understanding of different CAD tools (synthesis, lint, CDC, RDC, PrimeTime).

JOB DUTIES:

The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA and client internal IP's. Successful candidates will be responsible for leading, and participating in, the design of leading edge SoCs in advanced digital CMOS processes.

Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip definition, Architecture development and modeling, Development of micro-architectural specifications, Conversion of micro-architectural specifications to logic implementation, Verification, emulation, debug, synthesis, and timing closure, Interfacing with physical execution, software, and silicon bring-up teams.

EXPERIENCE AND EDUCATION:

SoC Design;

Knowledge AND hand-on experience from industry ASIC design flow including RTL coding, IP Integration, debugging/verification, and supporting synthesis and timing closure.

Experience with front end quality checks such as Lint, CDC, RDC. Running, Debugging, Reporting, Driving Cleanup.

Working knowledge of ARM cores and other I/O standard interfaces.

Roughly 10 years experience, but less is acceptable.

Bachelors in electrical engineering or computer engineering is preferred

An ideal candidate would also exhibit: Strong communication and documentation skills, Good organizational, time management and multitasking skills, Strong initiative and discipline to follow-through, Technical leadership

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Mandatory skills:

CAD tools, synthesis, lint, CDC, RDC, PrimeTime,

IP, ARM cores, Ethernet, DDR, DMA, PCIE, SATA,

SoC, SoC design, Chip definition, Architecture development and modeling,

RTL Design, ASIC design flow,

IP Integration, debugging, verification, synthesis,

physical execution, software, silicon bring-up, I/O interface,

micro architectural specifications, logic implementation, Verification, emulation, debug, synthesis

VIVA USA is an equal opportunity employer and is committed to maintaining a professional working environment that is free from discrimination and unlawful harassment. The Management, contractors, and staff of VIVA USA shall respect others without regard to race, sex, religion, age, color, creed, national or ethnic origin, physical, mental or sensory disability, marital status, sexual orientation, or status as a Vietnam-era, recently separated veteran, Active war time or campaign badge veteran, Armed forces service medal veteran, or disabled veteran. Please contact us at for any complaints, comments and suggestions.

Contact Details :

Account co-ordinator: Godwin D Antony Raj

VIVA USA INC.

3601 Algonquin Road, Suite 425

Rolling Meadows, IL 60008

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