Low Power Design Engineer

Job Title: Low Power Design Engineer

Location: Remote

Duration: 6+ months (Possible Extension-Long Term Project)

Description

• As a Low Power Design Engineer, you will have responsibilities spanning various aspects of low power for a hierarchical multi-voltage SOC design, and work in a cross-functional team with RTL, Synthesis, timing, and physical design engineers.

Requirements

• Must have strong concepts of Power Analysis and intent verification for digital designs.
• Must have strong experience writing UPF for multi-voltage hierarchical design at the block and top levels.
• Must have experience in power intent verification (preferably using Synopsys’s VCLP), and in a variety of methods to resolve power-intent violations.
• Must have experience using Power Analysis tools (preferably using Synopsys’s PrimePower).
• Strong understanding of Synthesis and Static Timing Analysis (STA) is highly desirable.
• Knowledge of RTL power analysis and reduction software (such as Ansys’s PowerArtist) is preferable.
• Must have strong communication skills.