Overview
On Site
$0.00/-
Accepts corp to corp applications
Contract - Independent
Contract - W2
Contract - to 2026-02-22
Skills
Management
Employment Authorization
SAP MM
LinkedIn
IPS
SERDES
PCI Express
DFT
ESD
Verilog
SystemVerilog
Change Data Capture
RDC
JTAG
RTL
Synopsys
Veritas Cluster Server
System On A Chip
Pure Data
SpyGlass
SANS
Debugging
Job Details
We have an immediate opportunity with one of our direct clients. Please find the job description below and if you are interested, please forward your resume and share below details:
Best contact number:
Work Authorization:
Hourly Payrate expected:
Month & Day of birth (MM/DD):
Present Location & Zip-code:
LinkedIn:
Title: RTL Design Engineer - DFX
Project Location: San Jose, CA - Hybrid (at least 3 days a week)
Duration: 12+ months contract
Senior RTL design engineer with strong DFT background is needed
SoC DFT architecture
Coding the DFT RTL using Verilog, JTAG/iJTAG
Gate level simulations
RTL simulations
RTL checks
TAP controller
Tops Skills:
RTL
DFX architecture
Verilog/System Verilog
RTL
DFX architecture
Verilog/System Verilog
This is a position for senior level RTL design engineer. As a part of the design team, candidate will be exposed to several IPs including Gbit SERDES, UCIe, PCIe I/F & high frequency design. Successful candidates will be participating in the DFX RTL coding/integration of leading edge I/O SoC in 3 nm processes.
This DFX RTL Design Engineer is expected to contribute in :
Implementation of SOC DFT features (TAP controller, GPIOs, ESD structures etc) into RTL using Verilog/system verilog, responsible for all RTL checks including lint/elab/CDC/RDC with 0-waivers, SOC level JTAG/IJTAG implementation (RTL/ICL/PDL), Gate level simulation using Synopsys VCS and Verdi, SOC-level SDC development and hand-off to PD, UPF development and hand-off to PD, Spyglass bringup and analysis for scan readiness/test coverage gaps.
Implementation of SOC DFT features (TAP controller, GPIOs, ESD structures etc) into RTL using Verilog/system verilog, responsible for all RTL checks including lint/elab/CDC/RDC with 0-waivers, SOC level JTAG/IJTAG implementation (RTL/ICL/PDL), Gate level simulation using Synopsys VCS and Verdi, SOC-level SDC development and hand-off to PD, UPF development and hand-off to PD, Spyglass bringup and analysis for scan readiness/test coverage gaps.
Candidate will also be engaged in silicon bring-up and debug as needed.
Candidate must have a BS in EE or CS. MS is a plus.
Candidate must have a BS in EE or CS. MS is a plus.
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.