RTL Design Engineer/Architect

Key Responsibilities

• Define and own the RTL architecture for high-speed and many lanes SERDES IPs.
• Lead RTL design, coding, and integration of SERDES blocks.
• Collaborate with analog, verification, PD, and validation teams to ensure seamless integration and successful silicon bring-up.
• Drive micro-architecture development, specification reviews, and design documentation.
• Perform lint, CDC, and synthesis checks to ensure design quality.
• Support post-silicon validation and debug efforts.
• Mentor junior engineers and provide technical leadership in design reviews.

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering or related field.
• 8+ years of experience in RTL design/architecture, with direct hands-on expertise in SERDES design(PAM4/NRZ, PCIe, Ethernet, CXL, etc.).
• Strong understanding of high-speed serial interfaces, clocking, and data-path architecture.
• Proficiency in Verilog/SystemVerilog for RTL coding.
• Proficiency in modelling with MATLAB.
• Solid knowledge of ASIC design flow, including synthesis, STA, and physical design considerations.
• Knowledge of simulation and verification methodologies (UVM, assertions, coverage).
• Strong analytical/debugging skills and ability to work cross-functionally.

Preferred Skills

• Experience with advanced process nodes.
• Familiarity with DFT, low-power design techniques, and ECO flows.
• Exposure to system-level architecture for networking, HPC, or data center applications.
• Strong communication and leadership skills.