Analog Layout Design Engineer

  • Santa Clara, CA
  • Posted 6 hours ago | Updated moments ago

Overview

On Site
USD 80 to 82
Accepts corp to corp applications
Contract - Independent
Contract - W2

Skills

Finfet
Analog
layout
designer
EDA
CMOS
ASIC
TSMC
Pyton
Synopsis

Job Details

Role: Analog Layout Design Engineer

Location: Santa Clara, CA

Emp Type: Contract

Interview: Phone/Skype

JOB DESCRIPTION

Minimum 7+ years of experience in Analog and RF layout.

Experience developing and leading complex layout IC for high-speed applications in advanced CMOS FinFET technologies such as 7nm and 3nm at the block level and chip level.

Experience developing and knowledge of complex layout IC for ultra-low power applications using advanced CMOS FinFET technologies for ASIC/SOC level designs

Thorough knowledge of industry standard EDA tools from Cadence, Mentor and Synopsys.

Experience with layout of high-performance high-speed analog mixed-signal blocks such TIAs, CMOS drivers, high-speed Data converters and PLLs.

Experience with floor planning, block level routing and top-level chip assembly.

Knowledge of layout techniques such as floor planning, layer generation, thermal aware layout with consideration for electro-migration.

Synopsys/Cadence/Mentor Layout tools (Preference: 5)

Python (Preference: 3)

TSMC 7nm or 5nm (Preference: 3)

TSMC 3nm (Preference: 5)

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