ASIC/RTL Design Engineer - Senior - Hybrid

  • San Jose, CA
  • Posted 42 days ago | Updated 9 days ago

Overview

Hybrid
$73.68 - $78.68
Contract - W2
Contract - 12 Month(s)

Skills

RTL coding
IP Integration
SoC Design
ASIC design
SoC architecture
debugging
verification
software
silicon
Ethernet
DDR
DMA
PCIE
SATA
Chip definition
Architecture development and modeling
micro architectural specification
implementation
emulation
debug
synthesis
communication
documentation
organizational
multitasking
Verilog
SystemVerilog
Low power design
Perl
Python
EDA tools
Cadence
Synopsys

Job Details

Title: ASIC/RTL Design Engineer - Senior

Description:

JOB DUTIES:

The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA and client internal IP's. Successful candidates will be responsible for leading, and participating in, the design of leading edge SoC's in advanced digital CMOS processes. Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip definition, Architecture development and modeling, Development of micro-architectural specifications, Conversion of micro-architectural specifications to logic implementation, Verification, emulation, debug, synthesis, and timing closure, Interfacing with physical execution, software, and silicon bring-up teams.


An ideal candidate would also exhibit: Strong communication and documentation skills, Good organizational, time management and multitasking skills, Strong initiative and discipline to follow-through, Technical leadership

EXPERIENCE AND EDUCATION:

SoC Design;
Knowledge AND hand-on experience from industry ASIC design flow including RTL coding, IP Integration, debugging/verification, and supporting synthesis and timing closure.
Working knowledge of ARM cores and other I/O standard interfaces.
Roughly 10 years experience, but less is acceptable.
Bachelors in electrical engineering or computer engineering is acceptable

Note :

3 days onsite is required

Mandatory skills:


RTL coding, IP Integration,
SoC Design, ASIC design, SoC architecture,
debugging, verification, software, silicon,
Ethernet, DDR, DMA, PCIE, SATA,
Chip definition, Architecture development and modeling, micro architectural specification,
implementation, Verification, emulation, debug, synthesis, communication, documentation, organizational, multitasking,
Verilog, SystemVerilog, Low power design, Perl, Python, EDA tools, Cadence, Synopsys

VIVA USA is an equal opportunity employer and is committed to maintaining a professional working environment that is free from discrimination and unlawful harassment. The Management, contractors, and staff of VIVA USA shall respect others without regard to race, sex, religion, age, color, creed, national or ethnic origin, physical, mental or sensory disability, marital status, sexual orientation, or status as a Vietnam-era, recently separated veteran, Active war time or campaign badge veteran, Armed forces service medal veteran, or disabled veteran. Please contact us at for any complaints, comments and suggestions.

Contact Details :


Account co-ordinator: Godwin D Antony Raj

VIVA USA INC.

3601 Algonquin Road, Suite 425
Rolling Meadows, IL 60008
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