Hardware Design Engineer 5

Job Title: Hardware Design Engineer 5 Location: Remote Employment Type: Contract (Only W2) Duration: 12 Years
About VLink: Started in 2006 and headquartered in Connecticut, VLink is one of the fastest growing digital technology services and consulting companies. Since its inception, our innovative team members have been solving the most complex business, and IT challenges of our global clients.
Job Description:
Candidate Requirements
Years of Experience Required: 10+ overall years of experience in the field.
Degrees or certifications required: BA in Engineering is required to be eligible for this role.
Disqualifiers: candidate lacking experience in System Verilog or UVM, particularly in creating and writing test benches will not be eligible for the role.
Best vs. Average: The ideal resume would contain proficiency in UVM testbench development and maintenance, strong knowledge of System Verilog, and excellent debugging skills for tests using waves and logs..
Performance Indicators: Performance will be assessed based on Task Delivery: Completing assigned tasks and meeting deadlines as per the schedule, Code Contributions: Regularly committing and landing code through pull requests, and Overall Schedule Adherence: Maintaining the project schedule and meeting deadlines.
Top 3 Hard Skills Required + Years of Experience
Recent years experience with UVM Testbench Development and Maintenance: Experience in creating and maintaining UVM testbenches..
Recent years experience with Strong Knowledge of System Verilog: Proficiency in coding with System Verilog..
Recent years experience with Debugging Skills: Ability to debug tests using waves and logs

"Summary:
Be part of a team working on design verification for complex IPs and sub-systems that are a part of modern FPGAs. Develop and execute verification test plans for IPs and/or sub-systems. This includes: development of testbench infrastructure, testcase creation, implementing checkers, writing functional coverage and assertions, develop common/reusable verification components for reuse across teams, perform coverage analysis and closure, run simulations and regressions, triage and debug test failures. Ideal candidate has extensive experience of IP level verification using UVM and System Verilog within the last 3 years. Knowledge of AMBA AXI protocol is preferred but not required.
Job Responsibilities:
Analyse information for project planning and execution.
Create and modify existing environments and components to verify features in a UVM simulation environment.
Build, test, and modify product prototypes using working models or theoretical models constructed with computer simulation.
Evaluate factors such as reporting formats required, constraints, and need for security restrictions to determine hardware configuration.
Monitor functioning of equipment and make necessary modifications to ensure system operates in conformance with specifications.
Skills:
Creativity, verbal and written communication skills, analytical and problem-solving ability.
Team player and detail oriented.
Basic knowledge of Verilog RTL programming language.
Advanced knowledge of UVM and System Verilog programming languages.
Basic knowledge of the practical application of engineering science and technology.
Basic knowledge of ASIC or FPGA based verification.
Previous experience with design related to hardware engineering field.

Education/Experience:
Bachelor's degree in engineering required.
10+ years experience required.

Employment Practices:
EEO, ADA, FMLA Compliant
VLink is an equal opportunity employer. At VLink, we are committed to embracing diversity, multiculturalism, and inclusion. VLink does not discriminate on the basis of race, color, religion, sex, national origin, disability status, protected veteran status, or any other characteristic protected by law. All aspects of employment including the decision to hire, promote, or discharge, will be decided on the basis of qualifications, merit, performance, and business needs.