Overview
USD 119,800.00 - 234,700.00 per year
Full Time
Skills
Network
Testing
FPGA
Microsoft Azure
Boost
Virtualization
Network Security
Management
Remote Direct Memory Access
Network Protocols
RTL
Collaboration
Accountability
Test Cases
Continuous Integration
Continuous Integration and Development
Continuous Delivery
Agile
Hosting
Sprint
UVM
Screening
PASS
Cloud Computing
Electrical Engineering
Computer Engineering
Hardware Development
Test Plans
SystemVerilog
Formal Verification
Scripting
Python
Windows PowerShell
Computer Networking
IPv4
IPv6
TCP
UDP
Computer Hardware
Integrated Circuit
IC
Internal Communications
Legal
Recruiting
Microsoft
Job Details
Microsoft Azure is building the fastest network in public cloud. We are seeking candidates who can span the stack from hardware to systems to applications, turning ideas into production systems at a rapid pace. Join us as a Senior Hardware Engineer to build the world's fastest public cloud and make a difference to millions of people across the planet.
As a Senior Verification Engineer in the Accelnet Hardware team, you will be responsible for building, testing, and deploying networking acceleration on Azure, and the largest deployment of Field-Programmable Gate Array (FPGA) SmartNICs (Azure Boost) in the world. You will develop the infrastructure for next-generation Software-Defined Networking (SDN), including arbitrary packet manipulations, reducing virtualization overhead, improving network security, enhancing connection establishment performance, and improving performance with Remote Direct Memory Access (RDMA) and custom network protocols. You should be able to drive projects with both hardware and software teams, both inside and outside of Microsoft.
This is a unique opportunity for a Senior Verification Engineer to see Register-Transfer Level (RTL) code go to production within weeks instead of years. Come help build one of the few truly hyperscale global clouds with innovations possible at every level of the computing stack.
Microsoft's mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.
Responsibilities:
Build scalable constrained random verification environment in system Verilog using prevalent verification methodologies.
Create comprehensive test plans to address functional scenarios in discussions with the software and hardware design teams.
Execute the test plan by adding testcases and tracking verification through coverage driven metrices.
Create and enhance verification environment by adding sequences, constraints, assertions, and functional coverage.
Scripts to automate and maintain execution of test suits to support continuous integration (CI) and continuous development (CD) flow.
Apply Agile development methodologies such as hosting code reviews, sprint planning, frequent deployment to cloud, and iterative development of features.
Handle occasional on-call responsibilities for addressing hardware issues reported by our customers.
Qualifications:
Required Qualifications:
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: ;br>
Microsoft will accept applications for the role until August 5, 2025.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form .
Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work. #azurecorejobs
As a Senior Verification Engineer in the Accelnet Hardware team, you will be responsible for building, testing, and deploying networking acceleration on Azure, and the largest deployment of Field-Programmable Gate Array (FPGA) SmartNICs (Azure Boost) in the world. You will develop the infrastructure for next-generation Software-Defined Networking (SDN), including arbitrary packet manipulations, reducing virtualization overhead, improving network security, enhancing connection establishment performance, and improving performance with Remote Direct Memory Access (RDMA) and custom network protocols. You should be able to drive projects with both hardware and software teams, both inside and outside of Microsoft.
This is a unique opportunity for a Senior Verification Engineer to see Register-Transfer Level (RTL) code go to production within weeks instead of years. Come help build one of the few truly hyperscale global clouds with innovations possible at every level of the computing stack.
Microsoft's mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.
Responsibilities:
Build scalable constrained random verification environment in system Verilog using prevalent verification methodologies.
Create comprehensive test plans to address functional scenarios in discussions with the software and hardware design teams.
Execute the test plan by adding testcases and tracking verification through coverage driven metrices.
Create and enhance verification environment by adding sequences, constraints, assertions, and functional coverage.
Scripts to automate and maintain execution of test suits to support continuous integration (CI) and continuous development (CD) flow.
Apply Agile development methodologies such as hosting code reviews, sprint planning, frequent deployment to cloud, and iterative development of features.
Handle occasional on-call responsibilities for addressing hardware issues reported by our customers.
Qualifications:
Required Qualifications:
- Bac h elor's Degree in Electrical Engineering, Computer Engineering, Mec h anical Engineering, or related field AND 5+ years technical engineering experience with Universal Verification Methodology (UVM), System Verilog and Verification Fundamentals
- OR Master's Degree in Electrical Engineering, Computer Engineering, Mec h anical Engineering, or related field AND 3+ years technical engineering experience with Universal Verification Methodology (UVM), System Verilog and Verification Fundamentals
- OR equivalent experience.
- 5+ years technical experience in hardware design verification, verification methodologies, or system Verilog.
- Ability to meet Microsoft, customer and/or government security screening requirements are required for t h is role. T h ese requirements include, but are not limited to t h e following specialized security screenings:
- Microsoft Cloud Background C h eck: T h is position will be required to pass t h e Microsoft Cloud Background C h eck upon h ire/transfer and every two years t h ereafter.
- Bac h elor's Degree in Electrical Engineering, Computer Engineering, Mec h anical Engineering, or related field AND 8+ years tec h nical engineering experience
- OR Master's Degree in Electrical Engineering, Computer Engineering, Mec h anical Engineering, or related field AND 6+ years technical engineering experience with hardware design verification, verification methodologies, and system Verilog.
- OR Doctorate Degree in Electrical Engineering, Computer Engineering, Mec h anical Engineering, or related field AND 3+ years technical engineering experience with hardware design verification, verification methodologies, and system Verilog
- OR equivalent experience.
- 8+ years of experience verifying designs at both unit and system levels, with a good understanding of constrained random verification principles and the ability to write comprehensive test plans.
- 1+ year(s) of experience with SystemVerilog, including constraints, functional coverage, and assertions, as well as familiarity with formal verification techniques.
- 1+ year(s) of experience with scripting languages such as Python or PowerShell, and knowledge of networking fundamentals including protocols like IPv4, IPv6, TCP, UDP, and DTLS.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: ;br>
Microsoft will accept applications for the role until August 5, 2025.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form .
Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work. #azurecorejobs
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.