Overview
Full Time
Skills
Analog Circuits
Wireless Communication
Innovation
RFIC
Cadence
calibre
Collaboration
Engineering Design
Layout
CMOS
Design For Manufacturability
Routing
Information Retrieval
International Relations
Investor Relations
ESD
LVS
Debugging
Integrated Circuit
RF
Job Details
Are you passionate about advancing the boundaries of RF analog circuit integration in advanced technology nodes for wireless transceivers? Do you thrive on innovation and improving RF layout methodologies? As an RFIC Layout Engineer, you will address intriguing daily layout challenges, collaborate with skilled RFIC design and layout teams, and continuously improve products to surpass previous iterations and enrich user experiences worldwide.
Description You will lay out detailed custom blocks, including floorplanning, placement, routing, and verification for high-frequency RF circuits, verifying and refining layouts through simulation to meet design requirements. You will diagnose sophisticated verification (DRC/LVS) and PDK issues using Cadence and Calibre. Collaboration with engineering design and layout teams will be meaningful to understand design concepts, constraints, and opportunities for improvement. Upon identifying challenges, you will propose solutions to streamline layout tasks, collaborating with teams to specify and finalize methodologies.
Minimum Qualifications
Preferred Qualifications
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .
Description You will lay out detailed custom blocks, including floorplanning, placement, routing, and verification for high-frequency RF circuits, verifying and refining layouts through simulation to meet design requirements. You will diagnose sophisticated verification (DRC/LVS) and PDK issues using Cadence and Calibre. Collaboration with engineering design and layout teams will be meaningful to understand design concepts, constraints, and opportunities for improvement. Upon identifying challenges, you will propose solutions to streamline layout tasks, collaborating with teams to specify and finalize methodologies.
Minimum Qualifications
- BS with 3 plus years of industry experience.
- Deep knowledge of sub-micron CMOS technologies (16nm, 7nm, and beyond) and proficiency with FinFet structures, guard-rings, deep N-wells, and PN junctions are required.
- Familiarity with sophisticated process effects such as LOD, WPE, and DFM is critical.
- Understanding trade-offs involving matching, parasitic effects, high-frequency routing, isolation, coupling, shielding, RC delay, EM, IR, ESD, and latch-up is vital.
Preferred Qualifications
- Experiences in sophisticated DRC, ERC, LVS verification, and debugging.
- Prior experiences in crafting custom layouts at the chip, block, and device levels, particularly for RF high-frequency circuits such as LNAs, mixers, VCOs, and PLLs is a plus.
- RF experience is helpful.
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.