Overview
Remote
Full Time
Part Time
Accepts corp to corp applications
Contract - W2
Contract - Independent
Contract - 9 month(s)
Skills
Deep expertise in SoC security architecture: Hardware Root-of-Trust
Secure Boot
Secure JTAG ARM TrustZone (normal + secure world isolation) Cryptographic accelerators (AES
SHA
RSA/ECC
PKE) TRNG
OTP/eFuses
anti-tamper
side-channel resistance Strong ARM CoreSight debug architecture experience: ETM/PTM trace
cross-trigger matrix
debug access port (DAP) Secure debug and authentication flows
Job Details
ASIC Engineer 100% Remote
Core Responsibilities
- Own ASIC/SoC micro-architecture and block-level definition for ARM-based high-performance SoCs
- Lead security, debug, and RAS (Reliability, Availability, Serviceability) feature definition and implementation
- Partner directly with customers to translate system requirements into detailed hardware specifications
- Drive architecture reviews, design reviews, and verification hand-off
- Collaborate with physical design, verification, firmware, and software teams through tape-out and silicon bring-up
- Author high-quality documentation (architecture specs, design guides, customer presentations)
Required Technical Expertise (Must-Have)
- 7+ years of hands-on ASIC/SoC RTL design through tape-out (Verilog/SystemVerilog)
- Multiple shipped ARM-based SoCs (Cortex-A, Cortex-R, Neoverse, or custom ARM CPU subsystems)
- Deep expertise in SoC security architecture: Hardware Root-of-Trust, Secure Boot, Secure JTAG ARM TrustZone (normal + secure world isolation) Cryptographic accelerators (AES, SHA, RSA/ECC, PKE) TRNG, OTP/eFuses, anti-tamper, side-channel resistance
- Strong ARM CoreSight debug architecture experience: ETM/PTM trace, cross-trigger matrix, debug access port (DAP) Secure debug and authentication flows
- Solid RAS implementation experience: ECC, parity, poison propagation, error logging/reporting Fault injection, interconnect/fabric error management (CHI, AXI, CXL experience a plus)
- Full-chip integration ownership (clocks, resets, power management, DFT)
- Proficiency with industry-standard flows: Lint, CDC, UPF, STA constraints
Preferred Skills & Background
- Chiplet / multi-die integration experience (UCIe, BoW, proprietary D2D)
- Datacenter or AI accelerator SoC experience
- Low-power design techniques and UPF power intent
- Experience presenting directly to customers and leading technical discussions
- Stable career history with 2 4 employers max in the last 10 years
- Prior success in small/startup environments ( 150 employees) strongly preferred
Education
- BS in Electrical Engineering or Computer Engineering required
- MS or PhD preferred (not mandatory if experience is exceptional)
Cultural & Team Fit
- Self-starter who thrives with broad ownership and minimal process overhead
- Excellent communication you will regularly present to customers and executive staff
- Team player who enjoys mentoring junior engineers while still staying hands-on
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