RTL Design Engineer - Onsite

Title: RTL Design Engineer - Onsite

Description:

JOB DUTIES:

Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level architectural specification.
Write microarchitecture specification for new and modified functions. Responsible for linting and simulation of design. Work with synthesis and backend teams for physical implementation.

EDUCATION:

Bachelor's or Master's in Computer Engineering

KEY RESPONSIBILITIES:
Perform RTL design of digital components in Verilog/systemverilog.
Analyze/fix Lint and CDC errors of the components.
Guarantee quality/timely deliverables meeting project s schedule.
Help to improve/automate design process.

PREFERRED EXPERIENCE:
Knowledge of RISK-V processor integration Express
Multi-clock domain designs.
Design constraints for synthesis and static timing analysis.
Knowledge of AXI/AMBA protocol
Knowledge of front-end RTL design tools and methodologies.
Knowledge of scripting languages?like?Perl, tcl or cshell

Mandatory skills:

RISK V processor integration,
AXI protocol, AMBA protocol,
Perl, tcl, cshell,
Verilog HDL, Verilog, systemverilog,
microarchitecture specification, project schedule, design process,
FPGA, ASIC, SoC, System on Chip

VIVA USA is an equal opportunity employer and is committed to maintaining a professional working environment that is free from discrimination and unlawful harassment. The Management, contractors, and staff of VIVA USA shall respect others without regard to race, sex, religion, age, color, creed, national or ethnic origin, physical, mental or sensory disability, marital status, sexual orientation, or status as a Vietnam-era, recently separated veteran, Active war time or campaign badge veteran, Armed forces service medal veteran, or disabled veteran. Please contact us at for any complaints, comments and suggestions.

Contact Details :

Account co-ordinator: Godwin D Antony Raj

VIVA USA INC.
3601 Algonquin Road, Suite 425
Rolling Meadows, IL 60008
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