Design Verification Engineer

  • San Jose, CA
  • Posted 60+ days ago | Updated 2 days ago

Overview

On Site
Hybrid
$140,000 - $240,000
Full Time
10% Travel

Skills

UVM
SoC
PCIe

Job Details

Role: Design Verification Engineers

(SoC-5, PCIe-5)Location:

Bay AreaSalary: 160-240k (DOE)

Free health insurancePTOs: 10 Business days (Including sick leaves)

Key Skills: UVM, SoC, PCIe, High Bandwidth memory, Emulation (Zebu or Palladium)

Job Description:

Architect block and full-chip verification environments using HVLs and constrained random
techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, SVA
Develop test plans and coverage metrics from specifications and write block and chip-level
tests in C,SV,UVM
Debug RTL and Gate simulations and work with design engineers to verify fixes.
Replicate silicon bugs in simulation environments and validate fixes or SW workarounds.
Convert verification tests to test patterns and assist Test Engineers on ATE vector bringup.
Evaluate latest verification methodologies and develop scripts etc. to automate verification
flows.

Key Skills: UVM, SoC, PCIe, High Bandwidth memory, Emulation (Zebu or Palladium)

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