SystemC/TLM2 Modeling & Verification Engineer

We are seeking a highly experienced Modeling & Verification Engineer with strong expertise in SystemC/TLM. The ideal candidate will play a key role in Performance Modeling/Verification.

Responsibilities:

• Develop, enhance, and maintain SystemC/TLM2 models for memory controllers, peripherals, and interconnects to accurately simulate hardware behavior and performance.
• Collaborate with cross-functional teams to integrate models into system-level design tools, ensuring functionality and performance alignment.
• Analyze models to identify bottlenecks and performance issues; implement optimizations to meet design specifications.
• Develop and execute testbenches for validating model functionality and correctness; support system-level testing and debugging.
• Produce clear documentation including model usage guidelines and design specifications.

Deliverables:

• Cycle-approximate performance models
• SV/UVM functional and performance verification

Required Skills & Experience:

• 5+ years of proven modeling & verification experience in large ASIC development projects, or software/firmware development in hardware environments.
• Strong C/C++ programming background in Linux environments.
• Proficiency in debugging tools (GDB, Valgrind) with solid debugging skills.
• Knowledge of Perl, Makefiles.
• Experience in Verilog/SystemVerilog/SystemC (preferred).
• Hands-on experience with C/Verilog environments using DPI/PLI (preferred).
• Strong analytical skills and attention to detail.
• Excellent written and verbal communication skills.
• Knowledge of PCIe & AXI (preferred).