HAPS Validation Engineer

  • San Jose, CA
  • Posted 24 days ago | Updated 4 days ago

Overview

On Site
Depends on Experience
Full Time

Skills

HAPS
Validation
FPGA

Job Details

Job Description:

key responsibilities

  • Help set up FPGA/Emulation platform (Synopsys HAPS) and device modeling
  • Help set up FPGA/Emulation debugging tools
  • Help modify the SoC design for the FPGA platform;
  • Duties include modeling, debugging, verification and SW support
  • Work with SoC design engineers, verification team, systems team and software engineering to perform early prototyping, debug issues and identify fixes; and
  • Support test program development, chip validation, and chip life until production maturity.

Qualifications

  • Knowledge of RTL logic design (Verilog), strong experience working with FPGAs. Familiarity with PCIe, USB, Ethernet, ARM, and other commonly used blocks in SoC designs;
  • Strong experience working with FPGA tools like Vivaldo
  • Familarity with Synopsys HAPS FPGA system
  • Good communication skills.
  • BS or MS (preferred) degree in EE/EECS/CS or equivalent.
  • 5 plus years of working experience